66 lines
2.2 KiB
LLVM
66 lines
2.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IV
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define <vscale x 1 x i64> @access_fixed_object(ptr %val) {
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; RV64IV-LABEL: access_fixed_object:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -528
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; RV64IV-NEXT: .cfi_def_cfa_offset 528
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; RV64IV-NEXT: addi a1, sp, 8
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; RV64IV-NEXT: vl1re64.v v8, (a1)
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; RV64IV-NEXT: ld a1, 520(sp)
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; RV64IV-NEXT: sd a1, 0(a0)
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; RV64IV-NEXT: addi sp, sp, 528
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; RV64IV-NEXT: ret
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%local = alloca i64
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%array = alloca [64 x i64]
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%v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %array
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%len = load i64, ptr %local
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store i64 %len, ptr %val
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ret <vscale x 1 x i64> %v
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}
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declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
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<vscale x 1 x i64>,
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<vscale x 1 x i64>,
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<vscale x 1 x i64>,
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i64);
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define <vscale x 1 x i64> @access_fixed_and_vector_objects(ptr %val) {
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; RV64IV-LABEL: access_fixed_and_vector_objects:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -528
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; RV64IV-NEXT: .cfi_def_cfa_offset 528
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 2 * vlenb
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; RV64IV-NEXT: addi a0, sp, 8
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; RV64IV-NEXT: vl1re64.v v8, (a0)
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; RV64IV-NEXT: addi a0, sp, 528
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; RV64IV-NEXT: ld a1, 520(sp)
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; RV64IV-NEXT: vl1re64.v v9, (a0)
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; RV64IV-NEXT: vsetvli zero, a1, e64, m1, ta, ma
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; RV64IV-NEXT: vadd.vv v8, v8, v9
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: slli a0, a0, 1
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; RV64IV-NEXT: add sp, sp, a0
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; RV64IV-NEXT: addi sp, sp, 528
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; RV64IV-NEXT: ret
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%local = alloca i64
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%vector = alloca <vscale x 1 x i64>
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%array = alloca [64 x i64]
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%v1 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %array
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%v2 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vector
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%len = load i64, ptr %local
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%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
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<vscale x 1 x i64> undef,
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<vscale x 1 x i64> %v1,
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<vscale x 1 x i64> %v2,
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i64 %len)
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ret <vscale x 1 x i64> %a
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}
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