77 lines
3.2 KiB
LLVM
77 lines
3.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix RV64
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; This used to crash during type legalization, where lowering (v4i1 =
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; BUILD_VECTOR) created a (v4i1 = SETCC v4i8) which during constant-folding
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; created illegally-typed i8 nodes. Ultimately, constant-folding failed and so
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; the new illegal nodes had no uses. However, during a second round of
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; legalization, this same pattern was generated from another BUILD_VECTOR. This
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; meant one of the illegally-typed (i8 = Constant<0>) nodes now had two dead
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; uses. Because the Constant and one of the uses were from round 1, they were
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; further up in the node order than the new second use, so the constant was
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; visited while it wasn't "dead". At the point of visiting the constant, we
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; crashed.
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define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lanes.b, <4 x i1> %sel) {
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; RV32-LABEL: constant_folding_crash:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: lw a0, 8(a0)
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; RV32-NEXT: vmv1r.v v10, v0
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; RV32-NEXT: vmv.v.x v11, a0
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; RV32-NEXT: vmsne.vi v0, v11, 0
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; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
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; RV32-NEXT: vmv.x.s a0, v8
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; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: vmv1r.v v0, v10
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; RV32-NEXT: vmerge.vim v8, v8, 1, v0
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; RV32-NEXT: vrgather.vi v9, v8, 0
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; RV32-NEXT: vmsne.vi v0, v9, 0
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; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV32-NEXT: vmv.v.i v8, 10
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; RV32-NEXT: vse32.v v8, (a0), v0.t
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; RV32-NEXT: ret
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;
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; RV64-LABEL: constant_folding_crash:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: ld a0, 8(a0)
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; RV64-NEXT: vmv1r.v v12, v0
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; RV64-NEXT: vmv.v.x v13, a0
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; RV64-NEXT: vmsne.vi v0, v13, 0
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; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
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; RV64-NEXT: vmv.x.s a0, v8
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; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vmv1r.v v0, v12
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; RV64-NEXT: vmerge.vim v8, v8, 1, v0
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; RV64-NEXT: vrgather.vi v9, v8, 0
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; RV64-NEXT: vmsne.vi v0, v9, 0
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; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV64-NEXT: vmv.v.i v8, 10
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; RV64-NEXT: vse32.v v8, (a0), v0.t
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; RV64-NEXT: ret
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entry:
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%sunkaddr = getelementptr i8, ptr %v54, i64 8
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%v56 = load i64, ptr %sunkaddr, align 8
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%trunc = and i64 %v56, 1
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%cmp = icmp eq i64 %trunc, 0
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%ptrs = select i1 %cmp, <4 x ptr> %lanes.a, <4 x ptr> %lanes.b
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%v67 = extractelement <4 x ptr> %ptrs, i64 0
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%mask = shufflevector <4 x i1> %sel, <4 x i1> undef, <4 x i32> zeroinitializer
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call void @llvm.masked.store.v4i32.p0(<4 x i32> <i32 10, i32 10, i32 10, i32 10>, ptr %v67, i32 16, <4 x i1> %mask)
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ret void
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}
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declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32, <4 x i1>)
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