24 lines
1,000 B
LLVM
24 lines
1,000 B
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s
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; There is no corresponding v1i256 type, so make sure we don't crash if we try
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; to lower via lowerBitreverseShuffle.
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define <256 x i1> @reverse_v256i1(<256 x i1> %a) {
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; CHECK-LABEL: reverse_v256i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 256
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; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: vrsub.vi v10, v10, -1
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; CHECK-NEXT: vrgather.vv v12, v8, v10
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: ret
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%res = call <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1> %a)
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ret <256 x i1> %res
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}
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declare <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1>)
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