543 lines
20 KiB
LLVM
543 lines
20 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
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declare <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16>, <2 x i1>, i32)
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define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i7_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i7> %v
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}
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declare <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15>, <2 x i1>, i32)
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define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i15:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i8> %v
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}
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declare <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16>, <2 x i1>, i32)
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define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
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ret <2 x i8> %v
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}
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declare <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16>, <128 x i1>, i32)
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define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v128i7_v128i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: li a1, 64
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; CHECK-NEXT: vslidedown.vi v12, v0, 8
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; CHECK-NEXT: mv a2, a0
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; CHECK-NEXT: bltu a0, a1, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a2, 64
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
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; CHECK-NEXT: addi a2, a0, -64
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; CHECK-NEXT: sltu a0, a0, a2
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: and a0, a0, a2
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; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
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; CHECK-NEXT: vmv1r.v v0, v12
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; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
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; CHECK-NEXT: li a0, 128
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vslideup.vx v8, v24, a1
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; CHECK-NEXT: ret
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%v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl)
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ret <128 x i7> %v
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}
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declare <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32>, <2 x i1>, i32)
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define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i32_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
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ret <2 x i8> %v
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}
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declare <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64>, <2 x i1>, i32)
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define <2 x i8> @vtrunc_v2i8_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i8> %v
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}
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define <2 x i8> @vtrunc_v2i8_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i8_v2i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
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ret <2 x i8> %v
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}
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declare <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32>, <2 x i1>, i32)
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define <2 x i16> @vtrunc_v2i16_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i16_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i16> %v
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}
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define <2 x i16> @vtrunc_v2i16_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i16_v2i32_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
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ret <2 x i16> %v
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}
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declare <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64>, <2 x i1>, i32)
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define <2 x i16> @vtrunc_v2i16_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i16_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i16> %v
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}
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define <2 x i16> @vtrunc_v2i16_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i16_v2i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
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ret <2 x i16> %v
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}
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declare <15 x i16> @llvm.vp.trunc.v15i16.v15i64(<15 x i64>, <15 x i1>, i32)
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define <15 x i16> @vtrunc_v15i16_v15i64(<15 x i64> %a, <15 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v15i16_v15i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <15 x i16> @llvm.vp.trunc.v15i16.v15i64(<15 x i64> %a, <15 x i1> %m, i32 %vl)
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ret <15 x i16> %v
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}
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declare <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64>, <2 x i1>, i32)
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define <2 x i32> @vtrunc_v2i32_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i32_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
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ret <2 x i32> %v
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}
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define <2 x i32> @vtrunc_v2i32_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v2i32_v2i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
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ret <2 x i32> %v
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}
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declare <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64>, <128 x i1>, i32)
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define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_v128i32_v128i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 6
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; CHECK-NEXT: sub sp, sp, a2
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb
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; CHECK-NEXT: vmv1r.v v4, v0
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: slli a2, a2, 5
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; CHECK-NEXT: add a2, sp, a2
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; CHECK-NEXT: addi a2, a2, 16
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; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: li a3, 40
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; CHECK-NEXT: mul a2, a2, a3
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; CHECK-NEXT: add a2, sp, a2
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; CHECK-NEXT: addi a2, a2, 16
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; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v1, v0, 8
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; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
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; CHECK-NEXT: vslidedown.vi v26, v0, 4
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; CHECK-NEXT: addi a2, a1, 512
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; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
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; CHECK-NEXT: vle64.v v8, (a2)
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|
|
; CHECK-NEXT: csrr a2, vlenb
|
||
|
|
; CHECK-NEXT: li a3, 48
|
||
|
|
; CHECK-NEXT: mul a2, a2, a3
|
||
|
|
; CHECK-NEXT: add a2, sp, a2
|
||
|
|
; CHECK-NEXT: addi a2, a2, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
|
||
|
|
; CHECK-NEXT: vslidedown.vi v27, v1, 4
|
||
|
|
; CHECK-NEXT: addi a2, a1, 640
|
||
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vle64.v v16, (a2)
|
||
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
||
|
|
; CHECK-NEXT: addi a2, a7, -64
|
||
|
|
; CHECK-NEXT: sltu a3, a7, a2
|
||
|
|
; CHECK-NEXT: addi a3, a3, -1
|
||
|
|
; CHECK-NEXT: and a4, a3, a2
|
||
|
|
; CHECK-NEXT: addi a2, a4, -32
|
||
|
|
; CHECK-NEXT: sltu a3, a4, a2
|
||
|
|
; CHECK-NEXT: addi a3, a3, -1
|
||
|
|
; CHECK-NEXT: and a3, a3, a2
|
||
|
|
; CHECK-NEXT: addi a2, a3, -16
|
||
|
|
; CHECK-NEXT: sltu a5, a3, a2
|
||
|
|
; CHECK-NEXT: addi a5, a5, -1
|
||
|
|
; CHECK-NEXT: and a2, a5, a2
|
||
|
|
; CHECK-NEXT: vslidedown.vi v0, v27, 2
|
||
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
|
||
|
|
; CHECK-NEXT: csrr a2, vlenb
|
||
|
|
; CHECK-NEXT: li a5, 24
|
||
|
|
; CHECK-NEXT: mul a2, a2, a5
|
||
|
|
; CHECK-NEXT: add a2, sp, a2
|
||
|
|
; CHECK-NEXT: addi a2, a2, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: li a2, 16
|
||
|
|
; CHECK-NEXT: addi a5, a1, 128
|
||
|
|
; CHECK-NEXT: bltu a3, a2, .LBB16_2
|
||
|
|
; CHECK-NEXT: # %bb.1:
|
||
|
|
; CHECK-NEXT: li a3, 16
|
||
|
|
; CHECK-NEXT: .LBB16_2:
|
||
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
||
|
|
; CHECK-NEXT: vslidedown.vi v28, v26, 2
|
||
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vle64.v v8, (a5)
|
||
|
|
; CHECK-NEXT: addi a5, sp, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: li a3, 64
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v27
|
||
|
|
; CHECK-NEXT: csrr a5, vlenb
|
||
|
|
; CHECK-NEXT: li a6, 48
|
||
|
|
; CHECK-NEXT: mul a5, a5, a6
|
||
|
|
; CHECK-NEXT: add a5, sp, a5
|
||
|
|
; CHECK-NEXT: addi a5, a5, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a5) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
|
||
|
|
; CHECK-NEXT: csrr a5, vlenb
|
||
|
|
; CHECK-NEXT: li a6, 56
|
||
|
|
; CHECK-NEXT: mul a5, a5, a6
|
||
|
|
; CHECK-NEXT: add a5, sp, a5
|
||
|
|
; CHECK-NEXT: addi a5, a5, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: bltu a7, a3, .LBB16_4
|
||
|
|
; CHECK-NEXT: # %bb.3:
|
||
|
|
; CHECK-NEXT: li a7, 64
|
||
|
|
; CHECK-NEXT: .LBB16_4:
|
||
|
|
; CHECK-NEXT: addi a5, a1, 384
|
||
|
|
; CHECK-NEXT: li a3, 32
|
||
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vle64.v v8, (a1)
|
||
|
|
; CHECK-NEXT: csrr a6, vlenb
|
||
|
|
; CHECK-NEXT: slli a6, a6, 3
|
||
|
|
; CHECK-NEXT: add a6, sp, a6
|
||
|
|
; CHECK-NEXT: addi a6, a6, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: addi a6, a7, -32
|
||
|
|
; CHECK-NEXT: sltu t0, a7, a6
|
||
|
|
; CHECK-NEXT: addi t0, t0, -1
|
||
|
|
; CHECK-NEXT: and a6, t0, a6
|
||
|
|
; CHECK-NEXT: addi t0, a6, -16
|
||
|
|
; CHECK-NEXT: sltu t1, a6, t0
|
||
|
|
; CHECK-NEXT: addi t1, t1, -1
|
||
|
|
; CHECK-NEXT: and t0, t1, t0
|
||
|
|
; CHECK-NEXT: vsetvli zero, t0, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v28
|
||
|
|
; CHECK-NEXT: addi t0, sp, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v16, (t0) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
|
||
|
|
; CHECK-NEXT: csrr t0, vlenb
|
||
|
|
; CHECK-NEXT: slli t0, t0, 4
|
||
|
|
; CHECK-NEXT: add t0, sp, t0
|
||
|
|
; CHECK-NEXT: addi t0, t0, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (t0) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: bltu a6, a2, .LBB16_6
|
||
|
|
; CHECK-NEXT: # %bb.5:
|
||
|
|
; CHECK-NEXT: li a6, 16
|
||
|
|
; CHECK-NEXT: .LBB16_6:
|
||
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
||
|
|
; CHECK-NEXT: vslidedown.vi v20, v1, 2
|
||
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vle64.v v8, (a5)
|
||
|
|
; CHECK-NEXT: addi a1, a1, 256
|
||
|
|
; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v26
|
||
|
|
; CHECK-NEXT: csrr a5, vlenb
|
||
|
|
; CHECK-NEXT: slli a5, a5, 3
|
||
|
|
; CHECK-NEXT: add a5, sp, a5
|
||
|
|
; CHECK-NEXT: addi a5, a5, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vnsrl.wi v16, v24, 0, v0.t
|
||
|
|
; CHECK-NEXT: csrr a5, vlenb
|
||
|
|
; CHECK-NEXT: li a6, 48
|
||
|
|
; CHECK-NEXT: mul a5, a5, a6
|
||
|
|
; CHECK-NEXT: add a5, sp, a5
|
||
|
|
; CHECK-NEXT: addi a5, a5, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: bltu a4, a3, .LBB16_8
|
||
|
|
; CHECK-NEXT: # %bb.7:
|
||
|
|
; CHECK-NEXT: li a4, 32
|
||
|
|
; CHECK-NEXT: .LBB16_8:
|
||
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vle64.v v24, (a1)
|
||
|
|
; CHECK-NEXT: addi a1, a4, -16
|
||
|
|
; CHECK-NEXT: sltu a5, a4, a1
|
||
|
|
; CHECK-NEXT: addi a5, a5, -1
|
||
|
|
; CHECK-NEXT: and a1, a5, a1
|
||
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v20
|
||
|
|
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
|
||
|
|
; CHECK-NEXT: bltu a4, a2, .LBB16_10
|
||
|
|
; CHECK-NEXT: # %bb.9:
|
||
|
|
; CHECK-NEXT: li a4, 16
|
||
|
|
; CHECK-NEXT: .LBB16_10:
|
||
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
||
|
|
; CHECK-NEXT: vslidedown.vi v5, v4, 2
|
||
|
|
; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v1
|
||
|
|
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
|
||
|
|
; CHECK-NEXT: vmv.v.v v0, v8
|
||
|
|
; CHECK-NEXT: bltu a7, a3, .LBB16_12
|
||
|
|
; CHECK-NEXT: # %bb.11:
|
||
|
|
; CHECK-NEXT: li a7, 32
|
||
|
|
; CHECK-NEXT: .LBB16_12:
|
||
|
|
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a4, 24
|
||
|
|
; CHECK-NEXT: mul a1, a1, a4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vmv4r.v v24, v8
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a4, 56
|
||
|
|
; CHECK-NEXT: mul a1, a1, a4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vslideup.vi v8, v24, 16
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a4, 56
|
||
|
|
; CHECK-NEXT: mul a1, a1, a4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: slli a1, a1, 4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vmv4r.v v24, v8
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a4, 48
|
||
|
|
; CHECK-NEXT: mul a1, a1, a4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vslideup.vi v8, v24, 16
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a4, 48
|
||
|
|
; CHECK-NEXT: mul a1, a1, a4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: vmv4r.v v8, v0
|
||
|
|
; CHECK-NEXT: vslideup.vi v8, v16, 16
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a4, 24
|
||
|
|
; CHECK-NEXT: mul a1, a1, a4
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
|
||
|
|
; CHECK-NEXT: addi a1, a7, -16
|
||
|
|
; CHECK-NEXT: sltu a4, a7, a1
|
||
|
|
; CHECK-NEXT: addi a4, a4, -1
|
||
|
|
; CHECK-NEXT: and a1, a4, a1
|
||
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v5
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: slli a1, a1, 5
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
|
||
|
|
; CHECK-NEXT: bltu a7, a2, .LBB16_14
|
||
|
|
; CHECK-NEXT: # %bb.13:
|
||
|
|
; CHECK-NEXT: li a7, 16
|
||
|
|
; CHECK-NEXT: .LBB16_14:
|
||
|
|
; CHECK-NEXT: vsetvli zero, a7, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v4
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a2, 40
|
||
|
|
; CHECK-NEXT: mul a1, a1, a2
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vnsrl.wi v16, v24, 0, v0.t
|
||
|
|
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vslideup.vi v16, v8, 16
|
||
|
|
; CHECK-NEXT: vse32.v v16, (a0)
|
||
|
|
; CHECK-NEXT: addi a1, a0, 256
|
||
|
|
; CHECK-NEXT: csrr a2, vlenb
|
||
|
|
; CHECK-NEXT: li a3, 24
|
||
|
|
; CHECK-NEXT: mul a2, a2, a3
|
||
|
|
; CHECK-NEXT: add a2, sp, a2
|
||
|
|
; CHECK-NEXT: addi a2, a2, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vse32.v v8, (a1)
|
||
|
|
; CHECK-NEXT: addi a1, a0, 128
|
||
|
|
; CHECK-NEXT: csrr a2, vlenb
|
||
|
|
; CHECK-NEXT: li a3, 48
|
||
|
|
; CHECK-NEXT: mul a2, a2, a3
|
||
|
|
; CHECK-NEXT: add a2, sp, a2
|
||
|
|
; CHECK-NEXT: addi a2, a2, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vse32.v v8, (a1)
|
||
|
|
; CHECK-NEXT: addi a0, a0, 384
|
||
|
|
; CHECK-NEXT: csrr a1, vlenb
|
||
|
|
; CHECK-NEXT: li a2, 56
|
||
|
|
; CHECK-NEXT: mul a1, a1, a2
|
||
|
|
; CHECK-NEXT: add a1, sp, a1
|
||
|
|
; CHECK-NEXT: addi a1, a1, 16
|
||
|
|
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
|
||
|
|
; CHECK-NEXT: vse32.v v8, (a0)
|
||
|
|
; CHECK-NEXT: csrr a0, vlenb
|
||
|
|
; CHECK-NEXT: slli a0, a0, 6
|
||
|
|
; CHECK-NEXT: add sp, sp, a0
|
||
|
|
; CHECK-NEXT: addi sp, sp, 16
|
||
|
|
; CHECK-NEXT: ret
|
||
|
|
%v = call <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64> %a, <128 x i1> %m, i32 %vl)
|
||
|
|
ret <128 x i32> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
declare <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64>, <32 x i1>, i32)
|
||
|
|
|
||
|
|
define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) {
|
||
|
|
; CHECK-LABEL: vtrunc_v32i32_v32i64:
|
||
|
|
; CHECK: # %bb.0:
|
||
|
|
; CHECK-NEXT: vmv8r.v v24, v8
|
||
|
|
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
|
||
|
|
; CHECK-NEXT: li a2, 16
|
||
|
|
; CHECK-NEXT: vslidedown.vi v12, v0, 2
|
||
|
|
; CHECK-NEXT: mv a1, a0
|
||
|
|
; CHECK-NEXT: bltu a0, a2, .LBB17_2
|
||
|
|
; CHECK-NEXT: # %bb.1:
|
||
|
|
; CHECK-NEXT: li a1, 16
|
||
|
|
; CHECK-NEXT: .LBB17_2:
|
||
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
|
||
|
|
; CHECK-NEXT: addi a1, a0, -16
|
||
|
|
; CHECK-NEXT: sltu a0, a0, a1
|
||
|
|
; CHECK-NEXT: addi a0, a0, -1
|
||
|
|
; CHECK-NEXT: and a0, a0, a1
|
||
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
|
||
|
|
; CHECK-NEXT: vmv1r.v v0, v12
|
||
|
|
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
|
||
|
|
; CHECK-NEXT: li a0, 32
|
||
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
|
||
|
|
; CHECK-NEXT: vslideup.vi v8, v24, 16
|
||
|
|
; CHECK-NEXT: ret
|
||
|
|
%v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl)
|
||
|
|
ret <32 x i32> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
declare <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8>, <2 x i1>, i32)
|
||
|
|
|
||
|
|
define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) {
|
||
|
|
; CHECK-LABEL: vtrunc_v2i7_v2i8:
|
||
|
|
; CHECK: # %bb.0:
|
||
|
|
; CHECK-NEXT: ret
|
||
|
|
%v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl)
|
||
|
|
ret <2 x i7> %v
|
||
|
|
}
|