255 lines
9 KiB
LLVM
255 lines
9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
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declare <vscale x 1 x half> @llvm.fabs.nxv1f16(<vscale x 1 x half>)
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define <vscale x 1 x half> @vfabs_nxv1f16(<vscale x 1 x half> %v) {
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; ZVFH-LABEL: vfabs_nxv1f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVFH-NEXT: vfabs.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfabs_nxv1f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v9, v9
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%r = call <vscale x 1 x half> @llvm.fabs.nxv1f16(<vscale x 1 x half> %v)
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ret <vscale x 1 x half> %r
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}
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declare <vscale x 2 x half> @llvm.fabs.nxv2f16(<vscale x 2 x half>)
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define <vscale x 2 x half> @vfabs_nxv2f16(<vscale x 2 x half> %v) {
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; ZVFH-LABEL: vfabs_nxv2f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; ZVFH-NEXT: vfabs.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfabs_nxv2f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v9, v9
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%r = call <vscale x 2 x half> @llvm.fabs.nxv2f16(<vscale x 2 x half> %v)
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ret <vscale x 2 x half> %r
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}
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declare <vscale x 4 x half> @llvm.fabs.nxv4f16(<vscale x 4 x half>)
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define <vscale x 4 x half> @vfabs_nxv4f16(<vscale x 4 x half> %v) {
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; ZVFH-LABEL: vfabs_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; ZVFH-NEXT: vfabs.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfabs_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v10, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
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; ZVFHMIN-NEXT: ret
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%r = call <vscale x 4 x half> @llvm.fabs.nxv4f16(<vscale x 4 x half> %v)
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ret <vscale x 4 x half> %r
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}
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declare <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half>)
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define <vscale x 8 x half> @vfabs_nxv8f16(<vscale x 8 x half> %v) {
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; ZVFH-LABEL: vfabs_nxv8f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; ZVFH-NEXT: vfabs.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfabs_nxv8f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v12, v12
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
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; ZVFHMIN-NEXT: ret
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%r = call <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half> %v)
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ret <vscale x 8 x half> %r
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}
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declare <vscale x 16 x half> @llvm.fabs.nxv16f16(<vscale x 16 x half>)
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define <vscale x 16 x half> @vfabs_nxv16f16(<vscale x 16 x half> %v) {
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; ZVFH-LABEL: vfabs_nxv16f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; ZVFH-NEXT: vfabs.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfabs_nxv16f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v16, v16
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
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; ZVFHMIN-NEXT: ret
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%r = call <vscale x 16 x half> @llvm.fabs.nxv16f16(<vscale x 16 x half> %v)
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ret <vscale x 16 x half> %r
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}
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declare <vscale x 32 x half> @llvm.fabs.nxv32f16(<vscale x 32 x half>)
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define <vscale x 32 x half> @vfabs_nxv32f16(<vscale x 32 x half> %v) {
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; ZVFH-LABEL: vfabs_nxv32f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
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; ZVFH-NEXT: vfabs.v v8, v8
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfabs_nxv32f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v16, v16
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; ZVFHMIN-NEXT: vfabs.v v16, v16
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
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; ZVFHMIN-NEXT: ret
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%r = call <vscale x 32 x half> @llvm.fabs.nxv32f16(<vscale x 32 x half> %v)
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ret <vscale x 32 x half> %r
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}
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declare <vscale x 1 x float> @llvm.fabs.nxv1f32(<vscale x 1 x float>)
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define <vscale x 1 x float> @vfabs_nxv1f32(<vscale x 1 x float> %v) {
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; CHECK-LABEL: vfabs_nxv1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 1 x float> @llvm.fabs.nxv1f32(<vscale x 1 x float> %v)
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ret <vscale x 1 x float> %r
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}
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declare <vscale x 2 x float> @llvm.fabs.nxv2f32(<vscale x 2 x float>)
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define <vscale x 2 x float> @vfabs_nxv2f32(<vscale x 2 x float> %v) {
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; CHECK-LABEL: vfabs_nxv2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x float> @llvm.fabs.nxv2f32(<vscale x 2 x float> %v)
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ret <vscale x 2 x float> %r
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}
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declare <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float>)
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define <vscale x 4 x float> @vfabs_nxv4f32(<vscale x 4 x float> %v) {
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; CHECK-LABEL: vfabs_nxv4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %v)
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ret <vscale x 4 x float> %r
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}
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declare <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float>)
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define <vscale x 8 x float> @vfabs_nxv8f32(<vscale x 8 x float> %v) {
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; CHECK-LABEL: vfabs_nxv8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float> %v)
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ret <vscale x 8 x float> %r
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}
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declare <vscale x 16 x float> @llvm.fabs.nxv16f32(<vscale x 16 x float>)
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define <vscale x 16 x float> @vfabs_nxv16f32(<vscale x 16 x float> %v) {
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; CHECK-LABEL: vfabs_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 16 x float> @llvm.fabs.nxv16f32(<vscale x 16 x float> %v)
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ret <vscale x 16 x float> %r
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}
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declare <vscale x 1 x double> @llvm.fabs.nxv1f64(<vscale x 1 x double>)
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define <vscale x 1 x double> @vfabs_nxv1f64(<vscale x 1 x double> %v) {
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; CHECK-LABEL: vfabs_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 1 x double> @llvm.fabs.nxv1f64(<vscale x 1 x double> %v)
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ret <vscale x 1 x double> %r
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}
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declare <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double>)
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define <vscale x 2 x double> @vfabs_nxv2f64(<vscale x 2 x double> %v) {
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; CHECK-LABEL: vfabs_nxv2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %v)
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ret <vscale x 2 x double> %r
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}
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declare <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double>)
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define <vscale x 4 x double> @vfabs_nxv4f64(<vscale x 4 x double> %v) {
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; CHECK-LABEL: vfabs_nxv4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %v)
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ret <vscale x 4 x double> %r
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}
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declare <vscale x 8 x double> @llvm.fabs.nxv8f64(<vscale x 8 x double>)
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define <vscale x 8 x double> @vfabs_nxv8f64(<vscale x 8 x double> %v) {
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; CHECK-LABEL: vfabs_nxv8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vfabs.v v8, v8
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x double> @llvm.fabs.nxv8f64(<vscale x 8 x double> %v)
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ret <vscale x 8 x double> %r
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}
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