106 lines
3.3 KiB
LLVM
106 lines
3.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkg \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkg \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
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declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32(
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<vscale x 1 x i32>,
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<vscale x 1 x i32>,
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iXLen, iXLen);
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define <vscale x 1 x i32> @intrinsic_vgmul_vs_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vgmul_vs_nxv1i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
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; CHECK-NEXT: vgmul.vv v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32(
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<vscale x 1 x i32> %0,
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<vscale x 1 x i32> %1,
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iXLen %2, iXLen 2)
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ret <vscale x 1 x i32> %a
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}
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declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32(
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<vscale x 2 x i32>,
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<vscale x 2 x i32>,
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iXLen, iXLen);
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define <vscale x 2 x i32> @intrinsic_vgmul_vs_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vgmul_vs_nxv2i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
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; CHECK-NEXT: vgmul.vv v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32(
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<vscale x 2 x i32> %0,
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<vscale x 2 x i32> %1,
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iXLen %2, iXLen 2)
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ret <vscale x 2 x i32> %a
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}
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declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32(
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<vscale x 4 x i32>,
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<vscale x 4 x i32>,
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iXLen, iXLen);
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define <vscale x 4 x i32> @intrinsic_vgmul_vs_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vgmul_vs_nxv4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
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; CHECK-NEXT: vgmul.vv v8, v10
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32(
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<vscale x 4 x i32> %0,
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<vscale x 4 x i32> %1,
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iXLen %2, iXLen 2)
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ret <vscale x 4 x i32> %a
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}
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declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32(
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<vscale x 8 x i32>,
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<vscale x 8 x i32>,
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iXLen, iXLen);
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define <vscale x 8 x i32> @intrinsic_vgmul_vs_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vgmul_vs_nxv8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
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; CHECK-NEXT: vgmul.vv v8, v12
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32(
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<vscale x 8 x i32> %0,
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<vscale x 8 x i32> %1,
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iXLen %2, iXLen 2)
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ret <vscale x 8 x i32> %a
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}
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declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32(
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<vscale x 16 x i32>,
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<vscale x 16 x i32>,
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iXLen, iXLen);
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define <vscale x 16 x i32> @intrinsic_vgmul_vs_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vgmul_vs_nxv16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
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; CHECK-NEXT: vgmul.vv v8, v16
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32(
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<vscale x 16 x i32> %0,
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<vscale x 16 x i32> %1,
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iXLen %2, iXLen 2)
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ret <vscale x 16 x i32> %a
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}
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