297 lines
16 KiB
Text
297 lines
16 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv7-none-eabi -mcpu=cortex-m7 -O3 -run-pass=tbaa,pipeliner %s -o - | FileCheck %s
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.ll"
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7m-none-unknown-eabi"
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%struct.bar = type { i16, i16, i16, i16, i16, i16, i16, i16 }
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@bar = external local_unnamed_addr global [0 x %struct.bar], align 2
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define i32 @foo() local_unnamed_addr #0 {
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%lsr.iv = phi ptr [ %uglygep, %do.body ], [ getelementptr (i8, ptr @bar, i32 -16), %entry ]
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%count.0 = phi i32 [ 0, %entry ], [ %count.4, %do.body ]
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%uglygep1 = getelementptr i8, ptr %lsr.iv, i32 16
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%0 = load i16, ptr %uglygep1, align 2, !tbaa !0
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%conv = sext i16 %0 to i32
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%uglygep2 = getelementptr i8, ptr %uglygep1, i32 2
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%1 = load i16, ptr %uglygep2, align 2, !tbaa !5
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%conv2 = sext i16 %1 to i32
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%conv.frozen = freeze i32 %conv
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%conv2.frozen = freeze i32 %conv2
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%div = sdiv i32 %conv.frozen, %conv2.frozen
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%conv3 = trunc i32 %div to i16
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%2 = zext i16 %conv3 to i32
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%uglygep3 = getelementptr i8, ptr %uglygep1, i32 12
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%3 = trunc i32 %2 to i16
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store i16 %3, ptr %uglygep3, align 2, !tbaa !6
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%4 = mul i32 %div, %conv2.frozen
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%rem.decomposed = sub i32 %conv.frozen, %4
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%conv8 = trunc i32 %rem.decomposed to i16
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%5 = zext i16 %conv8 to i32
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%uglygep4 = getelementptr i8, ptr %uglygep1, i32 14
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%6 = trunc i32 %5 to i16
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store i16 %6, ptr %uglygep4, align 2, !tbaa !7
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%uglygep5 = getelementptr i8, ptr %uglygep1, i32 4
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%7 = load i16, ptr %uglygep5, align 2, !tbaa !8
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%8 = zext i16 %7 to i32
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%cmp.not = icmp ne i32 %8, %2
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%inc = zext i1 %cmp.not to i32
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%spec.select = add nsw i32 %count.0, %inc
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%uglygep6 = getelementptr i8, ptr %uglygep1, i32 6
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%9 = load i16, ptr %uglygep6, align 2, !tbaa !9
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%10 = zext i16 %9 to i32
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%cmp16.not = icmp ne i32 %10, %5
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%inc19 = zext i1 %cmp16.not to i32
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%count.2 = add nsw i32 %spec.select, %inc19
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%uglygep7 = getelementptr i8, ptr %uglygep1, i32 8
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%11 = load i16, ptr %uglygep7, align 2, !tbaa !10
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%12 = zext i16 %11 to i32
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%cmp24.not = icmp ne i32 %12, %2
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%inc27 = zext i1 %cmp24.not to i32
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%count.3 = add nsw i32 %count.2, %inc27
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%uglygep8 = getelementptr i8, ptr %uglygep1, i32 10
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%13 = load i16, ptr %uglygep8, align 2, !tbaa !11
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%14 = zext i16 %13 to i32
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%cmp32.not = icmp ne i32 %14, %5
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%inc35 = zext i1 %cmp32.not to i32
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%count.4 = add nsw i32 %count.3, %inc35
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%uglygep9 = getelementptr i8, ptr %uglygep1, i32 18
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%15 = load i16, ptr %uglygep9, align 2, !tbaa !5
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%tobool.not = icmp eq i16 %15, 0
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%uglygep = getelementptr i8, ptr %lsr.iv, i32 16
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br i1 %tobool.not, label %do.end, label %do.body
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do.end: ; preds = %do.body
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ret i32 %count.4
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}
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attributes #0 = { "target-cpu"="cortex-m7" }
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!0 = !{!1, !2, i64 0}
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!1 = !{!"bar", !2, i64 0, !2, i64 2, !2, i64 4, !2, i64 6, !2, i64 8, !2, i64 10, !2, i64 12, !2, i64 14}
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!2 = !{!"short", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!1, !2, i64 2}
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!6 = !{!1, !2, i64 12}
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!7 = !{!1, !2, i64 14}
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!8 = !{!1, !2, i64 4}
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!9 = !{!1, !2, i64 6}
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!10 = !{!1, !2, i64 8}
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!11 = !{!1, !2, i64 10}
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...
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---
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name: foo
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: rgpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 3, class: gpr, preferred-register: '' }
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- { id: 4, class: gpr, preferred-register: '' }
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- { id: 5, class: gpr, preferred-register: '' }
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- { id: 6, class: rgpr, preferred-register: '' }
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- { id: 7, class: rgpr, preferred-register: '' }
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- { id: 8, class: rgpr, preferred-register: '' }
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- { id: 9, class: rgpr, preferred-register: '' }
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- { id: 10, class: rgpr, preferred-register: '' }
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- { id: 11, class: rgpr, preferred-register: '' }
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- { id: 12, class: rgpr, preferred-register: '' }
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- { id: 13, class: rgpr, preferred-register: '' }
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- { id: 14, class: rgpr, preferred-register: '' }
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- { id: 15, class: rgpr, preferred-register: '' }
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- { id: 16, class: rgpr, preferred-register: '' }
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- { id: 17, class: gprnopc, preferred-register: '' }
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- { id: 18, class: rgpr, preferred-register: '' }
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- { id: 19, class: rgpr, preferred-register: '' }
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- { id: 20, class: gprnopc, preferred-register: '' }
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- { id: 21, class: rgpr, preferred-register: '' }
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- { id: 22, class: rgpr, preferred-register: '' }
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- { id: 23, class: gprnopc, preferred-register: '' }
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- { id: 24, class: rgpr, preferred-register: '' }
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- { id: 25, class: rgpr, preferred-register: '' }
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- { id: 26, class: gprnopc, preferred-register: '' }
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- { id: 27, class: rgpr, preferred-register: '' }
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- { id: 28, class: rgpr, preferred-register: '' }
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- { id: 29, class: gprnopc, preferred-register: '' }
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: foo
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm @bar
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; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2MOVi32imm]], 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY [[t2MOVi]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[t2SUBri]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.do.body:
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; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.5(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[t2LDRSH_PRE:%[0-9]+]]:rgpr, [[t2LDRSH_PRE1:%[0-9]+]]:gpr = t2LDRSH_PRE [[COPY1]], 16, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep1, !tbaa !0)
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; CHECK-NEXT: [[t2LDRSHi12_:%[0-9]+]]:rgpr = t2LDRSHi12 [[t2LDRSH_PRE1]], 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep2, !tbaa !5)
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; CHECK-NEXT: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[t2LDRSH_PRE]], [[t2LDRSHi12_]], 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[t2SDIV]], 0, 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2MLS:%[0-9]+]]:rgpr = t2MLS [[t2SDIV]], [[t2LDRSHi12_]], [[t2LDRSH_PRE]], 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2UXTH1:%[0-9]+]]:rgpr = t2UXTH [[t2MLS]], 0, 14 /* CC::al */, $noreg
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; CHECK-NEXT: t2STRHi12 [[t2MLS]], [[t2LDRSH_PRE1]], 14, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep4, !tbaa !7)
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; CHECK-NEXT: [[t2LDRHi12_:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 4, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep5, !tbaa !8)
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; CHECK-NEXT: t2CMPrr [[t2LDRHi12_]], [[t2UXTH]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[COPY]](tied-def 0)
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; CHECK-NEXT: [[t2LDRHi12_1:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 6, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep6, !tbaa !9)
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; CHECK-NEXT: t2CMPrr [[t2LDRHi12_1]], [[t2UXTH1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri]](tied-def 0)
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; CHECK-NEXT: [[t2LDRHi12_2:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 8, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep7, !tbaa !10)
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; CHECK-NEXT: t2CMPrr [[t2LDRHi12_2]], [[t2UXTH]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri1]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri1]](tied-def 0)
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; CHECK-NEXT: [[t2LDRHi12_3:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 10, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep8, !tbaa !11)
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; CHECK-NEXT: t2CMPrr [[t2LDRHi12_3]], [[t2UXTH1]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri2]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri2]](tied-def 0)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY [[t2ADDri3]]
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; CHECK-NEXT: [[t2LDRHi12_4:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE1]], 18, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep9, !tbaa !5)
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; CHECK-NEXT: t2CMPri [[t2LDRHi12_4]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: t2Bcc %bb.5, 0 /* CC::eq */, $cpsr
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; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4.do.body:
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; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, %48, %bb.4
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.3, %63, %bb.4
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; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, %48, %bb.4
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; CHECK-NEXT: [[PHI3:%[0-9]+]]:rgpr = PHI [[t2SDIV]], %bb.3, %53, %bb.4
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; CHECK-NEXT: t2STRHi12 [[PHI3]], [[PHI2]], 12, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep3, !tbaa !6)
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; CHECK-NEXT: [[t2LDRSH_PRE2:%[0-9]+]]:rgpr, [[t2LDRSH_PRE3:%[0-9]+]]:gpr = t2LDRSH_PRE [[PHI]], 16, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep1, align 2, !tbaa !0)
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; CHECK-NEXT: [[t2LDRSHi12_1:%[0-9]+]]:rgpr = t2LDRSHi12 [[t2LDRSH_PRE3]], 2, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep2, align 2, !tbaa !5)
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; CHECK-NEXT: [[t2LDRHi12_5:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 18, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep9, align 2, !tbaa !5)
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; CHECK-NEXT: [[t2LDRHi12_6:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 8, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep7, align 2, !tbaa !10)
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; CHECK-NEXT: [[t2LDRHi12_7:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 10, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep8, align 2, !tbaa !11)
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; CHECK-NEXT: [[t2SDIV1:%[0-9]+]]:rgpr = t2SDIV [[t2LDRSH_PRE2]], [[t2LDRSHi12_1]], 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2LDRHi12_8:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 4, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep5, align 2, !tbaa !8)
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; CHECK-NEXT: [[t2MLS1:%[0-9]+]]:rgpr = t2MLS [[t2SDIV1]], [[t2LDRSHi12_1]], [[t2LDRSH_PRE2]], 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2UXTH2:%[0-9]+]]:rgpr = t2UXTH [[t2SDIV1]], 0, 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2LDRHi12_9:%[0-9]+]]:gprnopc = t2LDRHi12 [[t2LDRSH_PRE3]], 6, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.uglygep6, align 2, !tbaa !9)
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; CHECK-NEXT: t2CMPrr [[t2LDRHi12_8]], [[t2UXTH2]], 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: [[t2UXTH3:%[0-9]+]]:rgpr = t2UXTH [[t2MLS1]], 0, 14 /* CC::al */, $noreg
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; CHECK-NEXT: [[t2ADDri4:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[PHI1]](tied-def 0)
|
||
|
|
; CHECK-NEXT: t2CMPrr [[t2LDRHi12_9]], [[t2UXTH3]], 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
; CHECK-NEXT: [[t2ADDri5:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri4]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri4]](tied-def 0)
|
||
|
|
; CHECK-NEXT: t2CMPrr [[t2LDRHi12_6]], [[t2UXTH2]], 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
; CHECK-NEXT: [[t2ADDri6:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri5]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri5]](tied-def 0)
|
||
|
|
; CHECK-NEXT: t2CMPrr [[t2LDRHi12_7]], [[t2UXTH3]], 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
; CHECK-NEXT: [[t2ADDri7:%[0-9]+]]:rgpr = t2ADDri [[t2ADDri6]], 1, 1 /* CC::ne */, $cpsr, $noreg, implicit [[t2ADDri6]](tied-def 0)
|
||
|
|
; CHECK-NEXT: t2CMPri [[t2LDRHi12_5]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[t2ADDri7]]
|
||
|
|
; CHECK-NEXT: t2STRHi12 [[t2MLS1]], [[t2LDRSH_PRE3]], 14, 14 /* CC::al */, $noreg :: (store unknown-size into %ir.uglygep4, align 2, !tbaa !7)
|
||
|
|
; CHECK-NEXT: t2Bcc %bb.4, 1 /* CC::ne */, $cpsr
|
||
|
|
; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg
|
||
|
|
; CHECK-NEXT: {{ $}}
|
||
|
|
; CHECK-NEXT: bb.5:
|
||
|
|
; CHECK-NEXT: successors: %bb.2(0x80000000)
|
||
|
|
; CHECK-NEXT: {{ $}}
|
||
|
|
; CHECK-NEXT: [[PHI4:%[0-9]+]]:gpr = PHI [[t2LDRSH_PRE1]], %bb.3, [[t2LDRSH_PRE3]], %bb.4
|
||
|
|
; CHECK-NEXT: [[PHI5:%[0-9]+]]:rgpr = PHI [[t2SDIV]], %bb.3, [[t2SDIV1]], %bb.4
|
||
|
|
; CHECK-NEXT: [[PHI6:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.3, [[COPY3]], %bb.4
|
||
|
|
; CHECK-NEXT: t2STRHi12 [[PHI5]], [[PHI4]], 12, 14 /* CC::al */, $noreg :: (store unknown-size into %ir.uglygep3, align 2, !tbaa !6)
|
||
|
|
; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
|
||
|
|
; CHECK-NEXT: {{ $}}
|
||
|
|
; CHECK-NEXT: bb.2.do.end:
|
||
|
|
; CHECK-NEXT: $r0 = COPY [[PHI6]]
|
||
|
|
; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||
|
|
bb.0.entry:
|
||
|
|
successors: %bb.1(0x80000000)
|
||
|
|
|
||
|
|
%6:rgpr = t2MOVi32imm @bar
|
||
|
|
%7:rgpr = t2SUBri killed %6, 16, 14 /* CC::al */, $noreg, $noreg
|
||
|
|
%8:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
|
||
|
|
%5:gpr = COPY %8
|
||
|
|
%4:gpr = COPY %7
|
||
|
|
|
||
|
|
bb.1.do.body:
|
||
|
|
successors: %bb.2(0x04000000), %bb.1(0x7c000000)
|
||
|
|
|
||
|
|
%0:gpr = PHI %4, %bb.0, %3, %bb.1
|
||
|
|
%1:rgpr = PHI %5, %bb.0, %2, %bb.1
|
||
|
|
%9:rgpr, %3:gpr = t2LDRSH_PRE %0, 16, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep1, !tbaa !0)
|
||
|
|
%10:rgpr = t2LDRSHi12 %3, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep2, !tbaa !5)
|
||
|
|
%13:rgpr = t2SDIV %9, %10, 14 /* CC::al */, $noreg
|
||
|
|
%14:rgpr = t2UXTH %13, 0, 14 /* CC::al */, $noreg
|
||
|
|
t2STRHi12 %13, %3, 12, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep3, !tbaa !6)
|
||
|
|
%15:rgpr = t2MLS %13, %10, %9, 14 /* CC::al */, $noreg
|
||
|
|
%16:rgpr = t2UXTH %15, 0, 14 /* CC::al */, $noreg
|
||
|
|
t2STRHi12 %15, %3, 14, 14 /* CC::al */, $noreg :: (store (s16) into %ir.uglygep4, !tbaa !7)
|
||
|
|
%17:gprnopc = t2LDRHi12 %3, 4, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep5, !tbaa !8)
|
||
|
|
t2CMPrr killed %17, %14, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
%19:rgpr = t2ADDri %1, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %1(tied-def 0)
|
||
|
|
%20:gprnopc = t2LDRHi12 %3, 6, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep6, !tbaa !9)
|
||
|
|
t2CMPrr killed %20, %16, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
%22:rgpr = t2ADDri %19, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %19(tied-def 0)
|
||
|
|
%23:gprnopc = t2LDRHi12 %3, 8, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep7, !tbaa !10)
|
||
|
|
t2CMPrr killed %23, %14, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
%25:rgpr = t2ADDri %22, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %22(tied-def 0)
|
||
|
|
%26:gprnopc = t2LDRHi12 %3, 10, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep8, !tbaa !11)
|
||
|
|
t2CMPrr killed %26, %16, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
%28:rgpr = t2ADDri %25, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %25(tied-def 0)
|
||
|
|
%2:gpr = COPY %28
|
||
|
|
%29:gprnopc = t2LDRHi12 %3, 18, 14 /* CC::al */, $noreg :: (load (s16) from %ir.uglygep9, !tbaa !5)
|
||
|
|
t2CMPri killed %29, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||
|
|
t2Bcc %bb.1, 1 /* CC::ne */, $cpsr
|
||
|
|
t2B %bb.2, 14 /* CC::al */, $noreg
|
||
|
|
|
||
|
|
bb.2.do.end:
|
||
|
|
$r0 = COPY %2
|
||
|
|
tBX_RET 14 /* CC::al */, $noreg, implicit $r0
|
||
|
|
|
||
|
|
...
|