203 lines
6.4 KiB
Text
203 lines
6.4 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
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# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
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--- |
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define void @test_and_i1() { ret void}
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define void @test_and_i8() { ret void }
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define void @test_and_i16() { ret void }
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define void @test_and_i27() { ret void }
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define void @test_and_i32() { ret void }
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define void @test_and_i42() { ret void }
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define void @test_and_i64() { ret void }
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...
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---
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name: test_and_i1
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_and_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
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; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET 0
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%0(s32) = COPY $edx
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%1(s1) = G_TRUNC %0(s32)
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%2(s1) = G_AND %1, %1
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%3:_(s32) = G_ANYEXT %2
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$eax = COPY %3
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RET 0
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...
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---
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name: test_and_i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_and_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
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; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET 0
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%0(s32) = COPY $edx
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%1(s8) = G_TRUNC %0(s32)
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%2(s8) = G_AND %1, %1
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%3:_(s32) = G_ANYEXT %2
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$eax = COPY %3
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RET 0
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...
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---
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name: test_and_i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_and_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
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; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET 0
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%0(s32) = COPY $edx
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%1(s16) = G_TRUNC %0(s32)
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%2(s16) = G_AND %1, %1
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%3:_(s32) = G_ANYEXT %2
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$eax = COPY %3
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RET 0
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...
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---
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name: test_and_i27
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_and_i27
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY]]
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; CHECK-NEXT: $eax = COPY [[AND]](s32)
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; CHECK-NEXT: RET 0
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%0(s32) = COPY $edx
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%1(s27) = G_TRUNC %0(s32)
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%2(s27) = G_AND %1, %1
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%3:_(s32) = G_ANYEXT %2
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$eax = COPY %3
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RET 0
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...
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---
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name: test_and_i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_and_i32
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF1]]
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; CHECK-NEXT: $eax = COPY [[AND]](s32)
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; CHECK-NEXT: RET 0
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%0(s32) = IMPLICIT_DEF
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%1(s32) = IMPLICIT_DEF
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%2(s32) = G_AND %0, %1
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$eax = COPY %2
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RET 0
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...
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---
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name: test_and_i42
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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; X64-LABEL: name: test_and_i42
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; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
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; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY]]
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; X64-NEXT: $rax = COPY [[AND]](s64)
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; X64-NEXT: RET 0
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; X86-LABEL: name: test_and_i42
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; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
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; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV2]]
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; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV3]]
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; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
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; X86-NEXT: $rax = COPY [[MV]](s64)
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; X86-NEXT: RET 0
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%0(s64) = COPY $rdx
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%1(s42) = G_TRUNC %0(s64)
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%2(s42) = G_AND %1, %1
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%3:_(s64) = G_ANYEXT %2
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$rax = COPY %3
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RET 0
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...
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---
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name: test_and_i64
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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; X64-LABEL: name: test_and_i64
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; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
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; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
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; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF1]]
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; X64-NEXT: $rax = COPY [[AND]](s64)
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; X64-NEXT: RET 0
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; X86-LABEL: name: test_and_i64
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; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
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; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
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; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
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; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
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; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV2]]
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; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV3]]
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; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
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; X86-NEXT: $rax = COPY [[MV]](s64)
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; X86-NEXT: RET 0
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%0(s64) = IMPLICIT_DEF
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%1(s64) = IMPLICIT_DEF
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%2(s64) = G_AND %0, %1
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$rax = COPY %2
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RET 0
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...
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