260 lines
7.8 KiB
Text
260 lines
7.8 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
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# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
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--- |
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define void @test_mul_i1() { ret void }
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define i8 @test_mul_i8(i8 %arg1, i8 %arg2) {
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%ret = mul i8 %arg1, %arg2
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ret i8 %ret
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}
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define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
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%ret = mul i16 %arg1, %arg2
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ret i16 %ret
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}
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define i27 @test_mul_i27(i27 %arg1, i27 %arg2) {
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%ret = mul i27 %arg1, %arg2
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ret i27 %ret
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}
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define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {
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%ret = mul i32 %arg1, %arg2
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ret i32 %ret
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}
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define i42 @test_mul_i42(i42 %arg1, i42 %arg2) {
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%ret = mul i42 %arg1, %arg2
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ret i42 %ret
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}
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define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {
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%ret = mul i64 %arg1, %arg2
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ret i64 %ret
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}
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...
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---
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name: test_mul_i1
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_mul_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]]
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[MUL]], [[C]]
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; CHECK-NEXT: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
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; CHECK-NEXT: RET 0
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%0(s32) = COPY $edx
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%1(s1) = G_TRUNC %0(s32)
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%2(s1) = G_MUL %1, %1
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%3:_(p0) = G_IMPLICIT_DEF
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G_STORE %2, %3 :: (store (s1))
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RET 0
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...
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---
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name: test_mul_i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_mul_i8
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; CHECK: liveins: $edi, $esi
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dl
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: $al = COPY [[MUL]](s8)
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; CHECK-NEXT: RET 0, implicit $al
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%0(s8) = COPY $dl
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%1(s8) = COPY $sil
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%2(s8) = G_MUL %0, %1
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: test_mul_i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_mul_i16
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; CHECK: liveins: $edi, $esi
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: $ax = COPY [[MUL]](s16)
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; CHECK-NEXT: RET 0, implicit $ax
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%0(s16) = COPY $di
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%1(s16) = COPY $si
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%2(s16) = G_MUL %0, %1
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: test_mul_i27
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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;
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;
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; CHECK-LABEL: name: test_mul_i27
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY]]
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; CHECK-NEXT: $eax = COPY [[MUL]](s32)
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; CHECK-NEXT: RET 0
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%0(s32) = COPY $edx
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%1(s27) = G_TRUNC %0(s32)
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%2(s27) = G_MUL %1, %1
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%3:_(s32) = G_ANYEXT %2
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$eax = COPY %3
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RET 0
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...
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---
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name: test_mul_i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_mul_i32
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; CHECK: liveins: $edi, $esi
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
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; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: $eax = COPY [[MUL]](s32)
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; CHECK-NEXT: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s32) = G_MUL %0, %1
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_mul_i42
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; X64-LABEL: name: test_mul_i42
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; X64: liveins: $rdi, $rsi
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; X64-NEXT: {{ $}}
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; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
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; X64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY]]
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; X64-NEXT: $rax = COPY [[MUL]](s64)
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; X64-NEXT: RET 0
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; X86-LABEL: name: test_mul_i42
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; X86: liveins: $rdi, $rsi
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; X86-NEXT: {{ $}}
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; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
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; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; X86-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]]
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; X86-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]
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; X86-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
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; X86-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]]
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; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
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; X86-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
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; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32)
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; X86-NEXT: $rax = COPY [[MV]](s64)
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; X86-NEXT: RET 0
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%0(s64) = COPY $rdx
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%1(s42) = G_TRUNC %0(s64)
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%2(s42) = G_MUL %1, %1
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%3:_(s64) = G_ANYEXT %2
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$rax = COPY %3
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RET 0
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...
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---
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name: test_mul_i64
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; X64-LABEL: name: test_mul_i64
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; X64: liveins: $rdi, $rsi
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; X64-NEXT: {{ $}}
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; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; X64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; X64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
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; X64-NEXT: $rax = COPY [[MUL]](s64)
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; X64-NEXT: RET 0, implicit $rax
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; X86-LABEL: name: test_mul_i64
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; X86: liveins: $rdi, $rsi
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; X86-NEXT: {{ $}}
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; X86-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; X86-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
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; X86-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV2]]
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; X86-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]
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; X86-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
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; X86-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[UV]], [[UV2]]
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; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
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; X86-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
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; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MUL]](s32), [[ADD1]](s32)
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; X86-NEXT: $rax = COPY [[MV]](s64)
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; X86-NEXT: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_MUL %0, %1
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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