246 lines
11 KiB
Text
246 lines
11 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX1
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512F
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=AVX512BW
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# TODO: add tests for additional configuration after the legalization supported
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--- |
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define void @test_sub_v64i8() {
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%ret = sub <64 x i8> undef, undef
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ret void
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}
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define void @test_sub_v32i16() {
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%ret = sub <32 x i16> undef, undef
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ret void
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}
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define void @test_sub_v16i32() {
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%ret = sub <16 x i32> undef, undef
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ret void
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}
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define void @test_sub_v8i64() {
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%ret = sub <8 x i64> undef, undef
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ret void
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}
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...
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---
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name: test_sub_v64i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; AVX1-LABEL: name: test_sub_v64i8
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; AVX1: liveins: $zmm0, $zmm1
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; AVX1-NEXT: {{ $}}
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; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
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; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
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; AVX1-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>), [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
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; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>), [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
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; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV]], [[UV4]]
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; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV1]], [[UV5]]
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; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV2]], [[UV6]]
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; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<16 x s8>) = G_SUB [[UV3]], [[UV7]]
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; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>), [[SUB2]](<16 x s8>), [[SUB3]](<16 x s8>)
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; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
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; AVX1-NEXT: RET 0
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;
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; AVX512F-LABEL: name: test_sub_v64i8
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; AVX512F: liveins: $zmm0, $zmm1
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; AVX512F-NEXT: {{ $}}
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; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
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; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
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; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[UV]], [[UV2]]
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; AVX512F-NEXT: [[SUB1:%[0-9]+]]:_(<32 x s8>) = G_SUB [[UV1]], [[UV3]]
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; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<32 x s8>), [[SUB1]](<32 x s8>)
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; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
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; AVX512F-NEXT: RET 0
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;
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; AVX512BW-LABEL: name: test_sub_v64i8
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; AVX512BW: liveins: $zmm0, $zmm1
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; AVX512BW-NEXT: {{ $}}
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; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
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; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
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; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
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; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<64 x s8>)
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; AVX512BW-NEXT: RET 0
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%0(<64 x s8>) = IMPLICIT_DEF
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%1(<64 x s8>) = IMPLICIT_DEF
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%2(<64 x s8>) = G_SUB %0, %1
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$zmm0 = COPY %2
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RET 0
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...
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---
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name: test_sub_v32i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; AVX1-LABEL: name: test_sub_v32i16
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; AVX1: liveins: $zmm0, $zmm1
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; AVX1-NEXT: {{ $}}
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; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
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; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
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; AVX1-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>), [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
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; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<8 x s16>), [[UV5:%[0-9]+]]:_(<8 x s16>), [[UV6:%[0-9]+]]:_(<8 x s16>), [[UV7:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
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; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV]], [[UV4]]
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; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV1]], [[UV5]]
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; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV2]], [[UV6]]
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; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<8 x s16>) = G_SUB [[UV3]], [[UV7]]
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; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>), [[SUB2]](<8 x s16>), [[SUB3]](<8 x s16>)
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; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
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; AVX1-NEXT: RET 0
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;
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; AVX512F-LABEL: name: test_sub_v32i16
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; AVX512F: liveins: $zmm0, $zmm1
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; AVX512F-NEXT: {{ $}}
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; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
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; AVX512F-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
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; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[UV]], [[UV2]]
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; AVX512F-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s16>) = G_SUB [[UV1]], [[UV3]]
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; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<16 x s16>), [[SUB1]](<16 x s16>)
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; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
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; AVX512F-NEXT: RET 0
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;
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; AVX512BW-LABEL: name: test_sub_v32i16
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; AVX512BW: liveins: $zmm0, $zmm1
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; AVX512BW-NEXT: {{ $}}
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; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
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; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
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; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
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; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<32 x s16>)
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; AVX512BW-NEXT: RET 0
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%0(<32 x s16>) = IMPLICIT_DEF
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%1(<32 x s16>) = IMPLICIT_DEF
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%2(<32 x s16>) = G_SUB %0, %1
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$zmm0 = COPY %2
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RET 0
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...
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---
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name: test_sub_v16i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; AVX1-LABEL: name: test_sub_v16i32
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; AVX1: liveins: $zmm0, $zmm1
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; AVX1-NEXT: {{ $}}
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; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
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; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
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; AVX1-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>), [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
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; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<4 x s32>), [[UV5:%[0-9]+]]:_(<4 x s32>), [[UV6:%[0-9]+]]:_(<4 x s32>), [[UV7:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
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; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV]], [[UV4]]
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; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV1]], [[UV5]]
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; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV2]], [[UV6]]
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; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<4 x s32>) = G_SUB [[UV3]], [[UV7]]
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; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>), [[SUB2]](<4 x s32>), [[SUB3]](<4 x s32>)
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; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
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; AVX1-NEXT: RET 0
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;
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; AVX512F-LABEL: name: test_sub_v16i32
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; AVX512F: liveins: $zmm0, $zmm1
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; AVX512F-NEXT: {{ $}}
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; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
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; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)
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; AVX512F-NEXT: RET 0
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;
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; AVX512BW-LABEL: name: test_sub_v16i32
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; AVX512BW: liveins: $zmm0, $zmm1
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; AVX512BW-NEXT: {{ $}}
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; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
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; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
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; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
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; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)
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; AVX512BW-NEXT: RET 0
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<16 x s32>) = IMPLICIT_DEF
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%2(<16 x s32>) = G_SUB %0, %1
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$zmm0 = COPY %2
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RET 0
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...
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---
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name: test_sub_v8i64
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $zmm1
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; AVX1-LABEL: name: test_sub_v8i64
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; AVX1: liveins: $zmm0, $zmm1
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; AVX1-NEXT: {{ $}}
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; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
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; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
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; AVX1-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>), [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
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; AVX1-NEXT: [[UV4:%[0-9]+]]:_(<2 x s64>), [[UV5:%[0-9]+]]:_(<2 x s64>), [[UV6:%[0-9]+]]:_(<2 x s64>), [[UV7:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
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; AVX1-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV]], [[UV4]]
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; AVX1-NEXT: [[SUB1:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV1]], [[UV5]]
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; AVX1-NEXT: [[SUB2:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV2]], [[UV6]]
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; AVX1-NEXT: [[SUB3:%[0-9]+]]:_(<2 x s64>) = G_SUB [[UV3]], [[UV7]]
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; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>), [[SUB2]](<2 x s64>), [[SUB3]](<2 x s64>)
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; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
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; AVX1-NEXT: RET 0
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;
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; AVX512F-LABEL: name: test_sub_v8i64
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; AVX512F: liveins: $zmm0, $zmm1
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; AVX512F-NEXT: {{ $}}
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; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
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; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
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; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)
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; AVX512F-NEXT: RET 0
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;
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; AVX512BW-LABEL: name: test_sub_v8i64
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; AVX512BW: liveins: $zmm0, $zmm1
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; AVX512BW-NEXT: {{ $}}
|
||
|
|
; AVX512BW-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
; AVX512BW-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
; AVX512BW-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
|
||
|
|
; AVX512BW-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)
|
||
|
|
; AVX512BW-NEXT: RET 0
|
||
|
|
%0(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
%1(<8 x s64>) = IMPLICIT_DEF
|
||
|
|
%2(<8 x s64>) = G_SUB %0, %1
|
||
|
|
$zmm0 = COPY %2
|
||
|
|
RET 0
|
||
|
|
|
||
|
|
...
|