211 lines
6.5 KiB
Text
211 lines
6.5 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -mtriple=x86_64 -verify-machineinstrs --run-pass=machine-cse -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define float @max(float noundef %a, float noundef %b) #0 {
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entry:
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%U = fcmp uno float %a, %b
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br i1 %U, label %UL, label %NU
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NU: ; preds = %entry
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%GT = fcmp ogt float %a, %b
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br i1 %GT, label %EXIT, label %NGT
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NGT: ; preds = %NU
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%LT = fcmp one float %a, %b
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br i1 %LT, label %EXIT, label %EQ
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EQ: ; preds = %NGT
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%bc = bitcast float %a to i32
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%cmp = icmp slt i32 %bc, 0
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%eq = select i1 %cmp, float %a, float %b
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br label %EXIT
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UL: ; preds = %entry
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%AU = fcmp uno float %a, %a
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br i1 %AU, label %EXIT, label %ULB
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ULB: ; preds = %UL
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br label %EXIT
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EXIT: ; preds = %ULB, %UL, %EQ, %NGT, %NU
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%res = phi float [ %a, %NU ], [ %b, %NGT ], [ %a, %UL ], [ %eq, %EQ ], [ %b, %ULB ]
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ret float %res
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}
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attributes #0 = { "target-cpu"="skylake" }
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...
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---
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name: max
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: true
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: fr32, preferred-register: '' }
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- { id: 1, class: fr32, preferred-register: '' }
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- { id: 2, class: fr32, preferred-register: '' }
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- { id: 3, class: fr32, preferred-register: '' }
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- { id: 4, class: gr32, preferred-register: '' }
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liveins:
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- { reg: '$xmm0', virtual-reg: '%2' }
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- { reg: '$xmm1', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: max
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.6(0x00000800), %bb.1(0x7ffff800)
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; CHECK-NEXT: liveins: $xmm0, $xmm1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fr32 = COPY $xmm0
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; CHECK-NEXT: nofpexcept VUCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
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; CHECK-NEXT: JCC_1 %bb.6, 10, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.NU:
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; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $eflags
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: JCC_1 %bb.8, 7, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.NGT:
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; CHECK-NEXT: successors: %bb.8(0x50000000), %bb.3(0x30000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: nofpexcept VUCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
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; CHECK-NEXT: JCC_1 %bb.8, 5, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.EQ:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[VMOVSS2DIrr:%[0-9]+]]:gr32 = VMOVSS2DIrr [[COPY1]]
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; CHECK-NEXT: TEST32rr [[VMOVSS2DIrr]], [[VMOVSS2DIrr]], implicit-def $eflags
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; CHECK-NEXT: JCC_1 %bb.5, 8, implicit $eflags
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4.EQ:
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; CHECK-NEXT: successors: %bb.5(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5.EQ:
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; CHECK-NEXT: successors: %bb.8(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY]], %bb.4, [[COPY1]], %bb.3
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; CHECK-NEXT: JMP_1 %bb.8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6.UL:
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; CHECK-NEXT: successors: %bb.8(0x00000800), %bb.7(0x7ffff800)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: nofpexcept VUCOMISSrr [[COPY1]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
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; CHECK-NEXT: JCC_1 %bb.8, 10, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7.ULB:
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; CHECK-NEXT: successors: %bb.8(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.8.EXIT:
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:fr32 = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2, [[PHI]], %bb.5, [[COPY1]], %bb.6, [[COPY]], %bb.7
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; CHECK-NEXT: $xmm0 = COPY [[PHI1]]
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; CHECK-NEXT: RET 0, $xmm0
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bb.0.entry:
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successors: %bb.4(0x00000800), %bb.1(0x7ffff800)
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liveins: $xmm0, $xmm1
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%3:fr32 = COPY $xmm1
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%2:fr32 = COPY $xmm0
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nofpexcept VUCOMISSrr %2, %3, implicit-def $eflags, implicit $mxcsr
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JCC_1 %bb.4, 10, implicit $eflags
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JMP_1 %bb.1
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bb.1.NU:
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successors: %bb.6(0x40000000), %bb.2(0x40000000)
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nofpexcept VUCOMISSrr %2, %3, implicit-def $eflags, implicit $mxcsr
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JCC_1 %bb.6, 7, implicit $eflags
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JMP_1 %bb.2
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bb.2.NGT:
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successors: %bb.6(0x50000000), %bb.3(0x30000000)
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nofpexcept VUCOMISSrr %2, %3, implicit-def $eflags, implicit $mxcsr
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JCC_1 %bb.6, 5, implicit $eflags
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JMP_1 %bb.3
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bb.3.EQ:
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successors: %bb.7(0x40000000), %bb.8(0x40000000)
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%4:gr32 = VMOVSS2DIrr %2
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TEST32rr %4, %4, implicit-def $eflags
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JCC_1 %bb.8, 8, implicit $eflags
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bb.7.EQ:
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successors: %bb.8(0x80000000)
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bb.8.EQ:
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successors: %bb.6(0x80000000)
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%0:fr32 = PHI %3, %bb.7, %2, %bb.3
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JMP_1 %bb.6
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bb.4.UL:
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successors: %bb.6(0x00000800), %bb.5(0x7ffff800)
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nofpexcept VUCOMISSrr %2, %2, implicit-def $eflags, implicit $mxcsr
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JCC_1 %bb.6, 10, implicit $eflags
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JMP_1 %bb.5
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bb.5.ULB:
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successors: %bb.6(0x80000000)
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bb.6.EXIT:
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%1:fr32 = PHI %2, %bb.1, %3, %bb.2, %0, %bb.8, %2, %bb.4, %3, %bb.5
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$xmm0 = COPY %1
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RET 0, $xmm0
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...
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