80 lines
3.3 KiB
ArmAsm
80 lines
3.3 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid tile (expected: za[0-7]h.d or za[0-7]v.d)
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ld1d {za8h.d[w12, 0]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list
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// CHECK-NEXT: ld1d {za8h.d[w12, 0]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1d {za[w12, 0]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
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// CHECK-NEXT: ld1d {za[w12, 0]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1d {za3h.s[w12, 0]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d
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// CHECK-NEXT: ld1d {za3h.s[w12, 0]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid vector select register (expected: w12-w15)
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ld1d {za0h.d[w11, 0]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
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// CHECK-NEXT: ld1d {za0h.d[w11, 0]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1d {za0h.d[w16, 0]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
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// CHECK-NEXT: ld1d {za0h.d[w16, 0]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid vector select offset (expected: 0-1)
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ld1d {za0h.d[w12]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
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// CHECK-NEXT: ld1d {za0h.d[w12]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1d {za0h.d[w12, 2]}, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
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// CHECK-NEXT: ld1d {za0h.d[w12, 2]}, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate (expected: p0-p7)
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ld1d {za0h.d[w12, 0]}, p8/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p8/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate qualifier (expected: /z)
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ld1d {za0h.d[w12, 0]}, p0/m, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/m, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid memory operands
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ld1d {za0h.d[w12, 0]}, p0/z, [w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/z, [w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1d {za0h.d[w12, 0]}, p0/z, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
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// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/z, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
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// CHECK-NEXT: ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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