80 lines
3.6 KiB
ArmAsm
80 lines
3.6 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfdot za.s[w8, 0, vgx4], {z1.h-z5.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z1.h-z5.h}, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfdot za.s[w8, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid single vector register
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bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z16.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector select register
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bfdot za.s[w7, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
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// CHECK-NEXT: bfdot za.s[w7, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
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// CHECK-NEXT: bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector select offset
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bfdot za.s[w8, -1, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
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// CHECK-NEXT: bfdot za.s[w8, -1, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
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// CHECK-NEXT: bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfdot za.s[w8, -1, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
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// CHECK-NEXT: bfdot za.s[w8, -1, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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bfdot za.h[w8, 0, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
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// CHECK-NEXT: bfdot za.h[w8, 0, vgx4], {z0.h-z3.h}, z0.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector lane index
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bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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