339 lines
10 KiB
ArmAsm
339 lines
10 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// ---------------------------------------------------------------------------//
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// Test 64-bit form (x0) and its aliases
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// ---------------------------------------------------------------------------//
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uqdecd x0
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// CHECK-INST: uqdecd x0
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// CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ffe0 <unknown>
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uqdecd x0, all
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// CHECK-INST: uqdecd x0
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// CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ffe0 <unknown>
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uqdecd x0, all, mul #1
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// CHECK-INST: uqdecd x0
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// CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ffe0 <unknown>
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uqdecd x0, all, mul #16
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// CHECK-INST: uqdecd x0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xff,0xff,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04ffffe0 <unknown>
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// ---------------------------------------------------------------------------//
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// Test 32-bit form (w0) and its aliases
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// ---------------------------------------------------------------------------//
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uqdecd w0
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// CHECK-INST: uqdecd w0
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// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0ffe0 <unknown>
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uqdecd w0, all
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// CHECK-INST: uqdecd w0
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// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0ffe0 <unknown>
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uqdecd w0, all, mul #1
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// CHECK-INST: uqdecd w0
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// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0ffe0 <unknown>
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uqdecd w0, all, mul #16
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// CHECK-INST: uqdecd w0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04efffe0 <unknown>
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uqdecd w0, pow2
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// CHECK-INST: uqdecd w0, pow2
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// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0fc00 <unknown>
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uqdecd w0, pow2, mul #16
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// CHECK-INST: uqdecd w0, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04effc00 <unknown>
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// ---------------------------------------------------------------------------//
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// Test vector form and aliases.
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// ---------------------------------------------------------------------------//
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uqdecd z0.d
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// CHECK-INST: uqdecd z0.d
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// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0cfe0 <unknown>
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uqdecd z0.d, all
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// CHECK-INST: uqdecd z0.d
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// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0cfe0 <unknown>
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uqdecd z0.d, all, mul #1
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// CHECK-INST: uqdecd z0.d
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// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0cfe0 <unknown>
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uqdecd z0.d, all, mul #16
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// CHECK-INST: uqdecd z0.d, all, mul #16
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// CHECK-ENCODING: [0xe0,0xcf,0xef,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04efcfe0 <unknown>
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uqdecd z0.d, pow2
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// CHECK-INST: uqdecd z0.d, pow2
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// CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0cc00 <unknown>
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uqdecd z0.d, pow2, mul #16
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// CHECK-INST: uqdecd z0.d, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04efcc00 <unknown>
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// ---------------------------------------------------------------------------//
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// Test all patterns for 64-bit form
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// ---------------------------------------------------------------------------//
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uqdecd x0, pow2
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// CHECK-INST: uqdecd x0, pow2
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// CHECK-ENCODING: [0x00,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fc00 <unknown>
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uqdecd x0, vl1
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// CHECK-INST: uqdecd x0, vl1
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// CHECK-ENCODING: [0x20,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fc20 <unknown>
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uqdecd x0, vl2
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// CHECK-INST: uqdecd x0, vl2
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// CHECK-ENCODING: [0x40,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fc40 <unknown>
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uqdecd x0, vl3
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// CHECK-INST: uqdecd x0, vl3
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// CHECK-ENCODING: [0x60,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fc60 <unknown>
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uqdecd x0, vl4
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// CHECK-INST: uqdecd x0, vl4
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// CHECK-ENCODING: [0x80,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fc80 <unknown>
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uqdecd x0, vl5
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// CHECK-INST: uqdecd x0, vl5
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// CHECK-ENCODING: [0xa0,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fca0 <unknown>
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uqdecd x0, vl6
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// CHECK-INST: uqdecd x0, vl6
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// CHECK-ENCODING: [0xc0,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fcc0 <unknown>
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uqdecd x0, vl7
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// CHECK-INST: uqdecd x0, vl7
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// CHECK-ENCODING: [0xe0,0xfc,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fce0 <unknown>
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uqdecd x0, vl8
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// CHECK-INST: uqdecd x0, vl8
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// CHECK-ENCODING: [0x00,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fd00 <unknown>
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uqdecd x0, vl16
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// CHECK-INST: uqdecd x0, vl16
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// CHECK-ENCODING: [0x20,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fd20 <unknown>
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uqdecd x0, vl32
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// CHECK-INST: uqdecd x0, vl32
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// CHECK-ENCODING: [0x40,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fd40 <unknown>
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uqdecd x0, vl64
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// CHECK-INST: uqdecd x0, vl64
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// CHECK-ENCODING: [0x60,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fd60 <unknown>
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uqdecd x0, vl128
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// CHECK-INST: uqdecd x0, vl128
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// CHECK-ENCODING: [0x80,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fd80 <unknown>
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uqdecd x0, vl256
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// CHECK-INST: uqdecd x0, vl256
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// CHECK-ENCODING: [0xa0,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fda0 <unknown>
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uqdecd x0, #14
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// CHECK-INST: uqdecd x0, #14
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// CHECK-ENCODING: [0xc0,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fdc0 <unknown>
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uqdecd x0, #15
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// CHECK-INST: uqdecd x0, #15
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// CHECK-ENCODING: [0xe0,0xfd,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fde0 <unknown>
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uqdecd x0, #16
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// CHECK-INST: uqdecd x0, #16
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// CHECK-ENCODING: [0x00,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fe00 <unknown>
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uqdecd x0, #17
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// CHECK-INST: uqdecd x0, #17
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// CHECK-ENCODING: [0x20,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fe20 <unknown>
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uqdecd x0, #18
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// CHECK-INST: uqdecd x0, #18
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// CHECK-ENCODING: [0x40,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fe40 <unknown>
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uqdecd x0, #19
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// CHECK-INST: uqdecd x0, #19
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// CHECK-ENCODING: [0x60,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fe60 <unknown>
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uqdecd x0, #20
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// CHECK-INST: uqdecd x0, #20
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// CHECK-ENCODING: [0x80,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fe80 <unknown>
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uqdecd x0, #21
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// CHECK-INST: uqdecd x0, #21
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// CHECK-ENCODING: [0xa0,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fea0 <unknown>
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uqdecd x0, #22
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// CHECK-INST: uqdecd x0, #22
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// CHECK-ENCODING: [0xc0,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fec0 <unknown>
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uqdecd x0, #23
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// CHECK-INST: uqdecd x0, #23
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// CHECK-ENCODING: [0xe0,0xfe,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0fee0 <unknown>
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uqdecd x0, #24
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// CHECK-INST: uqdecd x0, #24
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// CHECK-ENCODING: [0x00,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ff00 <unknown>
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uqdecd x0, #25
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// CHECK-INST: uqdecd x0, #25
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// CHECK-ENCODING: [0x20,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ff20 <unknown>
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uqdecd x0, #26
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// CHECK-INST: uqdecd x0, #26
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// CHECK-ENCODING: [0x40,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ff40 <unknown>
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uqdecd x0, #27
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// CHECK-INST: uqdecd x0, #27
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// CHECK-ENCODING: [0x60,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ff60 <unknown>
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uqdecd x0, #28
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// CHECK-INST: uqdecd x0, #28
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// CHECK-ENCODING: [0x80,0xff,0xf0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04f0ff80 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 0420bce0 <unknown>
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uqdecd z0.d
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// CHECK-INST: uqdecd z0.d
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// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
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// CHECK-ERROR: instruction requires: sve or sme
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// CHECK-UNKNOWN: 04e0cfe0 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 0420bce0 <unknown>
|
||
|
|
|
||
|
|
uqdecd z0.d, pow2, mul #16
|
||
|
|
// CHECK-INST: uqdecd z0.d, pow2, mul #16
|
||
|
|
// CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 04efcc00 <unknown>
|
||
|
|
|
||
|
|
movprfx z0, z7
|
||
|
|
// CHECK-INST: movprfx z0, z7
|
||
|
|
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 0420bce0 <unknown>
|
||
|
|
|
||
|
|
uqdecd z0.d, pow2
|
||
|
|
// CHECK-INST: uqdecd z0.d, pow2
|
||
|
|
// CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
|
||
|
|
// CHECK-ERROR: instruction requires: sve or sme
|
||
|
|
// CHECK-UNKNOWN: 04e0cc00 <unknown>
|