28 lines
1.1 KiB
ArmAsm
28 lines
1.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid predicate register
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bfmax z23.h, p8/m, z23.h, z13.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: bfmax z23.h, p8/m, z23.h, z13.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmax z23.h, p1/z, z23.h, z13.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmax z23.h, p1/z, z23.h, z13.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector suffix
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bfmax z23.h, p1/z, z23.s, z13.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmax z23.h, p1/z, z23.s, z13.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmax z23.s, z23.h, z13.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfmax z23.s, z23.h, z13.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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