38 lines
1.4 KiB
ArmAsm
38 lines
1.4 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector lane index
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bfmlslt z0.s, z0.h, z0.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmlslt z0.s, z0.h, z0.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmlslt z0.s, z0.h, z8.h[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmlslt z0.s, z0.h, z8.h[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector suffix
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bfmlslt z0.s, z0.s, z0.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfmlslt z0.s, z0.s, z0.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmlslt z23.d, z23.h, z13.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfmlslt z23.d, z23.h, z13.h[1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h[1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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