31 lines
1.1 KiB
ArmAsm
31 lines
1.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid predicate register
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orqv v0.2d, p11, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: orqv v0.2d, p11, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector register
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orqv v0.4h, p1, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: orqv v0.4h, p1, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orqv z1.s, p1, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: orqv z1.s, p1, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector suffix
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orqv v0.8h, p1, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: orqv v0.8h, p1, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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