37 lines
1.1 KiB
ArmAsm
37 lines
1.1 KiB
ArmAsm
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# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+e -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+e < %s \
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# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
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# This file provides a basic test for RV64E, checking that the expected
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# set of registers and instructions are accepted. It only tests instructions
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# that are not valid in RV32E.
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# CHECK-ASM-AND-OBJ: ld a4, 25(a5)
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ld x14, 25(x15)
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# CHECK-ASM-AND-OBJ: sd a2, 36(a3)
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sd a2, 36(a3)
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# CHECK-ASM-AND-OBJ: addiw a4, a5, 37
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addiw a4, a5, 37
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# CHECK-ASM-AND-OBJ: slliw t1, t1, 31
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slliw t1, t1, 31
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# CHECK-ASM-AND-OBJ: srliw a0, a4, 0
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srliw a0, a4, 0
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# CHECK-ASM-AND-OBJ: sraiw a1, sp, 15
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sraiw a1, sp, 15
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# CHECK-ASM-AND-OBJ: slliw t0, t1, 13
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slliw t0, t1, 13
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# CHECK-ASM-AND-OBJ: addw ra, zero, zero
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addw ra, zero, zero
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# CHECK-ASM-AND-OBJ: subw t0, t2, t1
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subw t0, t2, t1
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# CHECK-ASM-AND-OBJ: sllw a5, a4, a3
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sllw a5, a4, a3
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# CHECK-ASM-AND-OBJ: srlw a0, s0, t0
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srlw a0, s0, t0
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# CHECK-ASM-AND-OBJ: sraw t0, a3, zero
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sraw t0, a3, zero
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