397 lines
15 KiB
LLVM
397 lines
15 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -S -passes=gvn-hoist < %s | FileCheck %s
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; Checking gvn-hoist in case of indirect branches.
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%class.bar = type { i8*, %class.base* }
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%class.base = type { i32 (...)** }
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@bar = local_unnamed_addr global i32 ()* null, align 8
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@bar1 = local_unnamed_addr global i32 ()* null, align 8
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; Check that the bitcast is not hoisted because it is after an indirect call
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define i32 @foo(i32* nocapture readonly %i) {
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; CHECK-LABEL: define i32 @foo
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; CHECK-SAME: (ptr nocapture readonly [[I:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
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; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
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; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
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; CHECK-NEXT: [[DOTOFF:%.*]] = add i32 [[TMP0]], -1
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; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[DOTOFF]], 2
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; CHECK-NEXT: br i1 [[SWITCH]], label [[L1_PREHEADER:%.*]], label [[SW_DEFAULT:%.*]]
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; CHECK: l1.preheader:
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; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: br label [[L1:%.*]]
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; CHECK: l1:
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @bar, align 8
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; CHECK-NEXT: [[CALL:%.*]] = tail call i32 [[TMP1]]()
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; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: br label [[L1]]
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; CHECK: sw.default:
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; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr @bar1, align 8
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; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 [[TMP2]]()
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; CHECK-NEXT: br label [[L1_PREHEADER]]
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;
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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%0 = load i32, i32* %i, align 4
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%.off = add i32 %0, -1
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%switch = icmp ult i32 %.off, 2
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br i1 %switch, label %l1.preheader, label %sw.default
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l1.preheader: ; preds = %sw.default, %entry
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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br label %l1
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l1: ; preds = %l1.preheader, %l1
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%1 = load i32 ()*, i32 ()** @bar, align 8
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%call = tail call i32 %1()
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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br label %l1
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sw.default: ; preds = %entry
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%2 = load i32 ()*, i32 ()** @bar1, align 8
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%call2 = tail call i32 %2()
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br label %l1.preheader
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}
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; Any instruction inside an infinite loop will not be hoisted because
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; there is no path to exit of the function.
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define i32 @foo1(i32* nocapture readonly %i) {
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; CHECK-LABEL: define i32 @foo1
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; CHECK-SAME: (ptr nocapture readonly [[I:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
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; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
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; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
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; CHECK-NEXT: [[DOTOFF:%.*]] = add i32 [[TMP0]], -1
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; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[DOTOFF]], 2
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; CHECK-NEXT: br i1 [[SWITCH]], label [[L1_PREHEADER:%.*]], label [[SW_DEFAULT:%.*]]
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; CHECK: l1.preheader:
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; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: [[Y1:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: br label [[L1:%.*]]
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; CHECK: l1:
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; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @bar, align 8
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; CHECK-NEXT: [[Y2:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: [[CALL:%.*]] = tail call i32 [[TMP1]]()
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; CHECK-NEXT: br label [[L1]]
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; CHECK: sw.default:
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; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr @bar1, align 8
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; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 [[TMP2]]()
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; CHECK-NEXT: br label [[L1_PREHEADER]]
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;
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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%0 = load i32, i32* %i, align 4
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%.off = add i32 %0, -1
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%switch = icmp ult i32 %.off, 2
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br i1 %switch, label %l1.preheader, label %sw.default
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l1.preheader: ; preds = %sw.default, %entry
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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%y1 = load %class.base*, %class.base** %x, align 8
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br label %l1
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l1: ; preds = %l1.preheader, %l1
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%1 = load i32 ()*, i32 ()** @bar, align 8
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%y2 = load %class.base*, %class.base** %x, align 8
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%call = tail call i32 %1()
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br label %l1
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sw.default: ; preds = %entry
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%2 = load i32 ()*, i32 ()** @bar1, align 8
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%call2 = tail call i32 %2()
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br label %l1.preheader
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}
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; Check that bitcast is hoisted even when one of them is partially redundant.
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define i32 @test13(i32* %P, i8* %Ptr, i32* nocapture readonly %i) {
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; CHECK-LABEL: define i32 @test13
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; CHECK-SAME: (ptr [[P:%.*]], ptr [[PTR:%.*]], ptr nocapture readonly [[I:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
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; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
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; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK:%.*]], label %B2]
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; CHECK: B2:
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; CHECK-NEXT: store i32 4, ptr [[P]], align 4
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; CHECK-NEXT: br label [[BRBLOCK]]
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; CHECK: BrBlock:
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 42
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; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
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; CHECK: T:
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; CHECK-NEXT: ret i32 123
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; CHECK: F:
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; CHECK-NEXT: ret i32 1422
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;
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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indirectbr i8* %Ptr, [label %BrBlock, label %B2]
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B2:
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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store i32 4, i32 *%P
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br label %BrBlock
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BrBlock:
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%L = load i32, i32* %P
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%C = icmp eq i32 %L, 42
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br i1 %C, label %T, label %F
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T:
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ret i32 123
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F:
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ret i32 1422
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}
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; Check that the bitcast is not hoisted because anticipability
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; cannot be guaranteed here as one of the indirect branch targets
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; do not have the bitcast instruction.
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define i32 @test14(i32* %P, i8* %Ptr, i32* nocapture readonly %i) {
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; CHECK-LABEL: define i32 @test14
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; CHECK-SAME: (ptr [[P:%.*]], ptr [[PTR:%.*]], ptr nocapture readonly [[I:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
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; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
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; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK:%.*]], label [[B2:%.*]], label %T]
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; CHECK: B2:
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; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: store i32 4, ptr [[P]], align 4
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; CHECK-NEXT: br label [[BRBLOCK]]
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; CHECK: BrBlock:
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; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 42
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; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
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; CHECK: T:
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; CHECK-NEXT: [[PI:%.*]] = load i32, ptr [[I]], align 4
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; CHECK-NEXT: ret i32 [[PI]]
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; CHECK: F:
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; CHECK-NEXT: [[PL:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: ret i32 [[PL]]
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;
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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indirectbr i8* %Ptr, [label %BrBlock, label %B2, label %T]
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B2:
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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store i32 4, i32 *%P
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br label %BrBlock
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BrBlock:
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%L = load i32, i32* %P
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%C = icmp eq i32 %L, 42
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br i1 %C, label %T, label %F
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T:
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%pi = load i32, i32* %i, align 4
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ret i32 %pi
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F:
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%pl = load i32, i32* %P
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ret i32 %pl
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}
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; Check that the bitcast is not hoisted because of a cycle
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; due to indirect branches
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define i32 @test16(i32* %P, i8* %Ptr, i32* nocapture readonly %i) {
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; CHECK-LABEL: define i32 @test16
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; CHECK-SAME: (ptr [[P:%.*]], ptr [[PTR:%.*]], ptr nocapture readonly [[I:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
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; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
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; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
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; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK:%.*]], label %B2]
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; CHECK: B2:
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; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
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; CHECK-NEXT: store i32 [[TMP0]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[BRBLOCK]]
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; CHECK: BrBlock:
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; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 42
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; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
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; CHECK: T:
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; CHECK-NEXT: indirectbr ptr [[P]], [label [[BRBLOCK]], label %B2]
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; CHECK: F:
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; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK]], label %B2]
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;
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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indirectbr i8* %Ptr, [label %BrBlock, label %B2]
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B2:
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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%0 = load i32, i32* %i, align 4
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store i32 %0, i32 *%P
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br label %BrBlock
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BrBlock:
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%L = load i32, i32* %P
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%C = icmp eq i32 %L, 42
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br i1 %C, label %T, label %F
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T:
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indirectbr i32* %P, [label %BrBlock, label %B2]
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F:
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indirectbr i8* %Ptr, [label %BrBlock, label %B2]
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}
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@_ZTIi = external constant i8*
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; Check that an instruction is not hoisted out of landing pad (%lpad4)
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; Also within a landing pad no redundancies are removed by gvn-hoist,
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; however an instruction may be hoisted into a landing pad if
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; landing pad has direct branches (e.g., %lpad to %catch1, %catch)
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; This CFG has a cycle (%lpad -> %catch1 -> %lpad4 -> %lpad)
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define i32 @foo2(i32* nocapture readonly %i) local_unnamed_addr personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
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; CHECK-LABEL: define i32 @foo2
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; CHECK-SAME: (ptr nocapture readonly [[I:%.*]]) local_unnamed_addr personality ptr @__gxx_personality_v0 {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[CMP]], label [[TRY_CONT:%.*]], label [[IF_THEN:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: [[EXCEPTION:%.*]] = tail call ptr @__cxa_allocate_exception(i64 4) #[[ATTR1:[0-9]+]]
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast ptr [[EXCEPTION]] to ptr
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; CHECK-NEXT: store i32 [[TMP0]], ptr [[TMP1]], align 16
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; CHECK-NEXT: invoke void @__cxa_throw(ptr [[EXCEPTION]], ptr @_ZTIi, ptr null) #[[ATTR2:[0-9]+]]
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; CHECK-NEXT: to label [[UNREACHABLE:%.*]] unwind label [[LPAD:%.*]]
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; CHECK: lpad:
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; CHECK-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 }
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; CHECK-NEXT: catch ptr @_ZTIi
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; CHECK-NEXT: catch ptr null
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; CHECK-NEXT: [[BC1:%.*]] = add i32 [[TMP0]], 10
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; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0
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||
|
|
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1
|
||
|
|
; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.eh.typeid.for(ptr @_ZTIi) #[[ATTR1]]
|
||
|
|
; CHECK-NEXT: [[MATCHES:%.*]] = icmp eq i32 [[TMP4]], [[TMP5]]
|
||
|
|
; CHECK-NEXT: [[BC7:%.*]] = add i32 [[TMP0]], 10
|
||
|
|
; CHECK-NEXT: [[TMP6:%.*]] = tail call ptr @__cxa_begin_catch(ptr [[TMP3]]) #[[ATTR1]]
|
||
|
|
; CHECK-NEXT: [[BC4:%.*]] = add i32 [[TMP0]], 10
|
||
|
|
; CHECK-NEXT: br i1 [[MATCHES]], label [[CATCH1:%.*]], label [[CATCH:%.*]]
|
||
|
|
; CHECK: catch1:
|
||
|
|
; CHECK-NEXT: invoke void @__cxa_rethrow() #[[ATTR2]]
|
||
|
|
; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[LPAD4:%.*]]
|
||
|
|
; CHECK: catch:
|
||
|
|
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4
|
||
|
|
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
|
||
|
|
; CHECK-NEXT: tail call void @__cxa_end_catch()
|
||
|
|
; CHECK-NEXT: br label [[TRY_CONT]]
|
||
|
|
; CHECK: lpad4:
|
||
|
|
; CHECK-NEXT: [[TMP8:%.*]] = landingpad { ptr, i32 }
|
||
|
|
; CHECK-NEXT: cleanup
|
||
|
|
; CHECK-NEXT: [[BC5:%.*]] = add i32 [[TMP0]], 10
|
||
|
|
; CHECK-NEXT: tail call void @__cxa_end_catch() #[[ATTR1]]
|
||
|
|
; CHECK-NEXT: invoke void @__cxa_throw(ptr [[EXCEPTION]], ptr @_ZTIi, ptr null) #[[ATTR2]]
|
||
|
|
; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[LPAD]]
|
||
|
|
; CHECK: try.cont:
|
||
|
|
; CHECK-NEXT: [[K_0:%.*]] = phi i32 [ [[ADD]], [[CATCH]] ], [ 0, [[ENTRY:%.*]] ]
|
||
|
|
; CHECK-NEXT: [[BC6:%.*]] = add i32 [[TMP0]], 10
|
||
|
|
; CHECK-NEXT: ret i32 [[K_0]]
|
||
|
|
; CHECK: unreachable:
|
||
|
|
; CHECK-NEXT: [[BC2:%.*]] = add i32 [[TMP0]], 10
|
||
|
|
; CHECK-NEXT: ret i32 [[BC2]]
|
||
|
|
;
|
||
|
|
entry:
|
||
|
|
%0 = load i32, i32* %i, align 4
|
||
|
|
%cmp = icmp eq i32 %0, 0
|
||
|
|
br i1 %cmp, label %try.cont, label %if.then
|
||
|
|
|
||
|
|
if.then:
|
||
|
|
%exception = tail call i8* @__cxa_allocate_exception(i64 4) #2
|
||
|
|
%1 = bitcast i8* %exception to i32*
|
||
|
|
store i32 %0, i32* %1, align 16
|
||
|
|
invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #3
|
||
|
|
to label %unreachable unwind label %lpad
|
||
|
|
|
||
|
|
lpad:
|
||
|
|
%2 = landingpad { i8*, i32 }
|
||
|
|
catch i8* bitcast (i8** @_ZTIi to i8*)
|
||
|
|
catch i8* null
|
||
|
|
%bc1 = add i32 %0, 10
|
||
|
|
%3 = extractvalue { i8*, i32 } %2, 0
|
||
|
|
%4 = extractvalue { i8*, i32 } %2, 1
|
||
|
|
%5 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2
|
||
|
|
%matches = icmp eq i32 %4, %5
|
||
|
|
%bc7 = add i32 %0, 10
|
||
|
|
%6 = tail call i8* @__cxa_begin_catch(i8* %3) #2
|
||
|
|
br i1 %matches, label %catch1, label %catch
|
||
|
|
|
||
|
|
catch1:
|
||
|
|
%bc3 = add i32 %0, 10
|
||
|
|
invoke void @__cxa_rethrow() #3
|
||
|
|
to label %unreachable unwind label %lpad4
|
||
|
|
|
||
|
|
catch:
|
||
|
|
%bc4 = add i32 %0, 10
|
||
|
|
%7 = load i32, i32* %i, align 4
|
||
|
|
%add = add nsw i32 %7, 1
|
||
|
|
tail call void @__cxa_end_catch()
|
||
|
|
br label %try.cont
|
||
|
|
|
||
|
|
lpad4:
|
||
|
|
%8 = landingpad { i8*, i32 }
|
||
|
|
cleanup
|
||
|
|
%bc5 = add i32 %0, 10
|
||
|
|
tail call void @__cxa_end_catch() #2
|
||
|
|
invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #3
|
||
|
|
to label %unreachable unwind label %lpad
|
||
|
|
|
||
|
|
try.cont:
|
||
|
|
%k.0 = phi i32 [ %add, %catch ], [ 0, %entry ]
|
||
|
|
%bc6 = add i32 %0, 10
|
||
|
|
ret i32 %k.0
|
||
|
|
|
||
|
|
unreachable:
|
||
|
|
%bc2 = add i32 %0, 10
|
||
|
|
ret i32 %bc2
|
||
|
|
}
|
||
|
|
|
||
|
|
declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr
|
||
|
|
|
||
|
|
declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr
|
||
|
|
|
||
|
|
declare i32 @__gxx_personality_v0(...)
|
||
|
|
|
||
|
|
; Function Attrs: nounwind readnone
|
||
|
|
declare i32 @llvm.eh.typeid.for(i8*) #1
|
||
|
|
|
||
|
|
declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr
|
||
|
|
|
||
|
|
declare void @__cxa_end_catch() local_unnamed_addr
|
||
|
|
|
||
|
|
declare void @__cxa_rethrow() local_unnamed_addr
|
||
|
|
|
||
|
|
attributes #1 = { nounwind readnone }
|
||
|
|
attributes #2 = { nounwind }
|
||
|
|
attributes #3 = { noreturn }
|