bolt/deps/llvm-18.1.8/llvm/test/Transforms/InstCombine/2007-01-18-VectorInfLoop.ll

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2025-02-14 19:21:04 +01:00
; RUN: opt < %s -passes=instcombine -disable-output
define <4 x i32> @test(<4 x i32> %A) {
%B = xor <4 x i32> %A, < i32 -1, i32 -1, i32 -1, i32 -1 >
%C = and <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 >
ret <4 x i32> %C
}