329 lines
10 KiB
LLVM
329 lines
10 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -keep-loops=false -S < %s | FileCheck %s
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; RUN: opt -passes='simplifycfg<no-keep-loops>' -S < %s | FileCheck %s
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; It's not worthwhile to if-convert one of the phi nodes and leave
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; the other behind, because that still requires a branch. If
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; SimplifyCFG if-converts one of the phis, it should do both.
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define i32 @upper_bound(ptr %r, i32 %high, i32 %k) nounwind {
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; CHECK-LABEL: define i32 @upper_bound
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; CHECK-SAME: (ptr [[R:%.*]], i32 [[HIGH:%.*]], i32 [[K:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[HIGH_ADDR_0:%.*]] = phi i32 [ [[HIGH]], [[ENTRY:%.*]] ], [ [[SPEC_SELECT:%.*]], [[WHILE_BODY:%.*]] ]
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; CHECK-NEXT: [[LOW_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[SPEC_SELECT1:%.*]], [[WHILE_BODY]] ]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[LOW_0]], [[HIGH_ADDR_0]]
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; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOW_0]], [[HIGH_ADDR_0]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 2
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[DIV]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[K]], [[TMP0]]
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; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[DIV]], 1
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i32 [[DIV]], i32 [[HIGH_ADDR_0]]
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; CHECK-NEXT: [[SPEC_SELECT1]] = select i1 [[CMP1]], i32 [[LOW_0]], i32 [[ADD2]]
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; CHECK-NEXT: br label [[WHILE_COND]]
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; CHECK: while.end:
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; CHECK-NEXT: ret i32 [[LOW_0]]
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;
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entry:
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br label %while.cond
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while.cond: ; preds = %if.then, %if.else, %entry
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%high.addr.0 = phi i32 [ %high, %entry ], [ %div, %if.then ], [ %high.addr.0, %if.else ]
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%low.0 = phi i32 [ 0, %entry ], [ %low.0, %if.then ], [ %add2, %if.else ]
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%cmp = icmp ult i32 %low.0, %high.addr.0
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br i1 %cmp, label %while.body, label %while.end
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while.body: ; preds = %while.cond
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%add = add i32 %low.0, %high.addr.0
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%div = udiv i32 %add, 2
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%idxprom = zext i32 %div to i64
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%arrayidx = getelementptr inbounds i32, ptr %r, i64 %idxprom
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%0 = load i32, ptr %arrayidx
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%cmp1 = icmp ult i32 %k, %0
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br i1 %cmp1, label %if.then, label %if.else
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if.then: ; preds = %while.body
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br label %while.cond
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if.else: ; preds = %while.body
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%add2 = add i32 %div, 1
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br label %while.cond
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while.end: ; preds = %while.cond
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ret i32 %low.0
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}
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define i32 @merge0(i1 %c1, i1 %c2, i1 %c3) {
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; CHECK-LABEL: define i32 @merge0
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; CHECK-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]]) {
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; CHECK-NEXT: j2:
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; CHECK-NEXT: [[DOT:%.*]] = select i1 [[C2]], i32 0, i32 1
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[C3]], i32 2, i32 3
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; CHECK-NEXT: [[PHI2:%.*]] = select i1 [[C1]], i32 [[DOT]], i32 [[SPEC_SELECT]]
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; CHECK-NEXT: ret i32 [[PHI2]]
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;
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br i1 %c1, label %if1, label %else1
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if1:
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br i1 %c2, label %if2, label %else2
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if2:
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br label %j1 else2:
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br label %j1
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else1:
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br i1 %c3, label %j1, label %j2
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j1:
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%phi1 = phi i32 [ 0, %if2 ], [ 1, %else2 ], [ 2, %else1 ]
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br label %j2
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j2:
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%phi2 = phi i32 [ %phi1, %j1 ], [ 3, %else1 ]
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ret i32 %phi2
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}
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define i8 @merge1(i8 noundef %arg, i1 %c1, i1 %c2) {
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; CHECK-LABEL: define i8 @merge1
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; CHECK-SAME: (i8 noundef [[ARG:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i8 [[ARG]], label [[UNREACHABLE:%.*]] [
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; CHECK-NEXT: i8 -123, label [[CASE0:%.*]]
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; CHECK-NEXT: i8 66, label [[SUCC:%.*]]
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; CHECK-NEXT: i8 123, label [[CASE2:%.*]]
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; CHECK-NEXT: ]
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; CHECK: unreachable:
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; CHECK-NEXT: unreachable
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; CHECK: case0:
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; CHECK-NEXT: [[C1_NOT:%.*]] = xor i1 [[C1]], true
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; CHECK-NEXT: [[C2_NOT:%.*]] = xor i1 [[C2]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[C1_NOT]], i1 true, i1 [[C2_NOT]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[C1_NOT]], i8 0, i8 3
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[BRMERGE]], i8 [[DOTMUX]], i8 4
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: case2:
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: Succ:
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; CHECK-NEXT: [[PHI2:%.*]] = phi i8 [ 2, [[CASE2]] ], [ 1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[CASE0]] ]
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; CHECK-NEXT: ret i8 [[PHI2]]
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;
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entry:
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switch i8 %arg, label %unreachable [
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i8 -123, label %case0
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i8 66, label %case1
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i8 123, label %case2
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]
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unreachable:
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unreachable
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case0:
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br i1 %c1, label %CommonPred, label %BB
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case1:
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br label %BB
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case2:
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br label %BB
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CommonPred:
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br i1 %c2, label %Succ, label %BB
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BB:
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%phi1 = phi i8 [ 0, %case0 ], [1, %case1],[2, %case2],[3,%CommonPred]
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br label %Succ
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Succ:
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%phi2 = phi i8 [ %phi1, %BB ], [ 4, %CommonPred ]
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ret i8 %phi2
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}
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define i8 @merge1_unfoldable_one_block(i8 noundef %arg, i1 %c1, i1 %c2) {
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; CHECK-LABEL: define i8 @merge1_unfoldable_one_block
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; CHECK-SAME: (i8 noundef [[ARG:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i8 [[ARG]], label [[UNREACHABLE:%.*]] [
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; CHECK-NEXT: i8 -123, label [[CASE0:%.*]]
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; CHECK-NEXT: i8 66, label [[SUCC:%.*]]
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; CHECK-NEXT: i8 123, label [[CASE2:%.*]]
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; CHECK-NEXT: ]
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; CHECK: unreachable:
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; CHECK-NEXT: unreachable
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; CHECK: case0:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: [[C1_NOT:%.*]] = xor i1 [[C1]], true
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; CHECK-NEXT: [[C2_NOT:%.*]] = xor i1 [[C2]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[C1_NOT]], i1 true, i1 [[C2_NOT]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[C1_NOT]], i8 0, i8 3
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[BRMERGE]], i8 [[DOTMUX]], i8 4
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: case2:
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: Succ:
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; CHECK-NEXT: [[PHI2:%.*]] = phi i8 [ 2, [[CASE2]] ], [ 1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[CASE0]] ]
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; CHECK-NEXT: ret i8 [[PHI2]]
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;
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entry:
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switch i8 %arg, label %unreachable [
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i8 -123, label %case0
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i8 66, label %case1
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i8 123, label %case2
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]
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unreachable:
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unreachable
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case0:
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call void @dummy()
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br i1 %c1, label %CommonPred, label %BB
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case1:
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br label %BB
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case2:
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br label %BB
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CommonPred:
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br i1 %c2, label %Succ, label %BB
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BB:
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%phi1 = phi i8 [ 0, %case0 ], [1, %case1],[2, %case2],[3,%CommonPred]
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br label %Succ
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Succ:
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%phi2 = phi i8 [ %phi1, %BB ], [ 4, %CommonPred ]
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ret i8 %phi2
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}
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define i8 @merge1_unfoldable_two_block(i8 noundef %arg, i1 %c1, i1 %c2) {
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; CHECK-LABEL: define i8 @merge1_unfoldable_two_block
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; CHECK-SAME: (i8 noundef [[ARG:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i8 [[ARG]], label [[UNREACHABLE:%.*]] [
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; CHECK-NEXT: i8 -123, label [[CASE0:%.*]]
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; CHECK-NEXT: i8 66, label [[CASE1:%.*]]
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; CHECK-NEXT: i8 123, label [[SUCC:%.*]]
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; CHECK-NEXT: ]
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; CHECK: unreachable:
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; CHECK-NEXT: unreachable
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; CHECK: case0:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: [[C1_NOT:%.*]] = xor i1 [[C1]], true
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; CHECK-NEXT: [[C2_NOT:%.*]] = xor i1 [[C2]], true
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; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[C1_NOT]], i1 true, i1 [[C2_NOT]]
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; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[C1_NOT]], i8 0, i8 3
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[BRMERGE]], i8 [[DOTMUX]], i8 4
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: case1:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: Succ:
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; CHECK-NEXT: [[PHI2:%.*]] = phi i8 [ 1, [[CASE1]] ], [ 2, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[CASE0]] ]
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; CHECK-NEXT: ret i8 [[PHI2]]
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;
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entry:
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switch i8 %arg, label %unreachable [
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i8 -123, label %case0
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i8 66, label %case1
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i8 123, label %case2
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]
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unreachable:
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unreachable
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case0:
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call void @dummy()
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br i1 %c1, label %CommonPred, label %BB
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case1:
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call void @dummy()
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br label %BB
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case2:
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br label %BB
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CommonPred:
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br i1 %c2, label %Succ, label %BB
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BB:
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%phi1 = phi i8 [ 0, %case0 ], [1, %case1],[2, %case2],[3,%CommonPred]
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br label %Succ
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Succ:
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%phi2 = phi i8 [ %phi1, %BB ], [ 4, %CommonPred ]
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ret i8 %phi2
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}
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define i8 @merge1_unfoldable_all_block(i8 noundef %arg, i1 %c1, i1 %c2) {
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; CHECK-LABEL: define i8 @merge1_unfoldable_all_block
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; CHECK-SAME: (i8 noundef [[ARG:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i8 [[ARG]], label [[UNREACHABLE:%.*]] [
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; CHECK-NEXT: i8 -123, label [[CASE0:%.*]]
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; CHECK-NEXT: i8 66, label [[CASE1:%.*]]
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; CHECK-NEXT: i8 123, label [[CASE2:%.*]]
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; CHECK-NEXT: ]
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; CHECK: unreachable:
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; CHECK-NEXT: unreachable
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; CHECK: case0:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: br i1 [[C1]], label [[COMMONPRED:%.*]], label [[SUCC:%.*]]
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; CHECK: case1:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: case2:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: CommonPred:
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; CHECK-NEXT: call void @dummy()
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[C2]], i8 4, i8 3
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; CHECK-NEXT: br label [[SUCC]]
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; CHECK: Succ:
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; CHECK-NEXT: [[PHI2:%.*]] = phi i8 [ 0, [[CASE0]] ], [ 1, [[CASE1]] ], [ 2, [[CASE2]] ], [ [[SPEC_SELECT]], [[COMMONPRED]] ]
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; CHECK-NEXT: ret i8 [[PHI2]]
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;
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entry:
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switch i8 %arg, label %unreachable [
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i8 -123, label %case0
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i8 66, label %case1
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i8 123, label %case2
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]
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unreachable:
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unreachable
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case0:
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call void @dummy()
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br i1 %c1, label %CommonPred, label %BB
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case1:
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call void @dummy()
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br label %BB
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case2:
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call void @dummy()
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br label %BB
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CommonPred:
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call void @dummy()
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br i1 %c2, label %Succ, label %BB
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BB:
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%phi1 = phi i8 [ 0, %case0 ], [1, %case1],[2, %case2],[3,%CommonPred]
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br label %Succ
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Succ:
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%phi2 = phi i8 [ %phi1, %BB ], [ 4, %CommonPred ]
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ret i8 %phi2
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}
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declare void @dummy()
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