93 lines
3.3 KiB
LLVM
93 lines
3.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt < %s -passes=separate-const-offset-from-gep,slsr,gvn -S | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-unknown-unknown"
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; arr[i + 5]
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; arr[i * 2 + 5]
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; arr[i * 3 + 5]
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; arr[i * 4 + 5]
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;
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; => reassociate-geps
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;
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; *(&arr[i] + 5)
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; *(&arr[i * 2] + 5)
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; *(&arr[i * 3] + 5)
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; *(&arr[i * 4] + 5)
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;
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; => slsr
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;
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; p1 = &arr[i]
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; *(p1 + 5)
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; p2 = p1 + i
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; *(p2 + 5)
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; p3 = p2 + i
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; *(p3 + 5)
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; p4 = p3 + i
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; *(p4 + 5)
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define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) {
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; CHECK-LABEL: define void @slsr_after_reassociate_geps(
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; CHECK-SAME: ptr [[ARR:%.*]], i32 [[I:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[ARR]], i64 [[TMP1]]
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; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 20
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; CHECK-NEXT: [[V1:%.*]] = load float, ptr [[P12]], align 4
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; CHECK-NEXT: call void @foo(float [[V1]])
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; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP1]], 2
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP2]], i64 [[TMP3]]
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; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 20
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; CHECK-NEXT: [[V2:%.*]] = load float, ptr [[P24]], align 4
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; CHECK-NEXT: call void @foo(float [[V2]])
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP4]], i64 [[TMP3]]
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; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds i8, ptr [[TMP5]], i64 20
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; CHECK-NEXT: [[V3:%.*]] = load float, ptr [[P36]], align 4
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; CHECK-NEXT: call void @foo(float [[V3]])
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i64 [[TMP3]]
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; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 20
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; CHECK-NEXT: [[V4:%.*]] = load float, ptr [[P48]], align 4
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; CHECK-NEXT: call void @foo(float [[V4]])
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; CHECK-NEXT: ret void
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;
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; PTX-LABEL: .visible .func slsr_after_reassociate_geps(
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; PTX: ld.param.u64 [[arr:%rd[0-9]+]], [slsr_after_reassociate_geps_param_0];
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; PTX: ld.param.u32 [[i:%r[0-9]+]], [slsr_after_reassociate_geps_param_1];
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%i2 = shl nsw i32 %i, 1
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%i3 = mul nsw i32 %i, 3
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%i4 = shl nsw i32 %i, 2
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%j1 = add nsw i32 %i, 5
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%p1 = getelementptr inbounds float, ptr %arr, i32 %j1
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; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4;
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; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]];
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%v1 = load float, ptr %p1, align 4
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; PTX: ld.f32 {{%f[0-9]+}}, [[[base1]]+20];
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call void @foo(float %v1)
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%j2 = add nsw i32 %i2, 5
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%p2 = getelementptr inbounds float, ptr %arr, i32 %j2
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; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]];
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%v2 = load float, ptr %p2, align 4
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; PTX: ld.f32 {{%f[0-9]+}}, [[[base2]]+20];
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call void @foo(float %v2)
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%j3 = add nsw i32 %i3, 5
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%p3 = getelementptr inbounds float, ptr %arr, i32 %j3
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; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]];
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%v3 = load float, ptr %p3, align 4
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; PTX: ld.f32 {{%f[0-9]+}}, [[[base3]]+20];
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call void @foo(float %v3)
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%j4 = add nsw i32 %i4, 5
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%p4 = getelementptr inbounds float, ptr %arr, i32 %j4
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; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]];
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%v4 = load float, ptr %p4, align 4
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; PTX: ld.f32 {{%f[0-9]+}}, [[[base4]]+20];
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call void @foo(float %v4)
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ret void
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}
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declare void @foo(float)
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