1567 lines
85 KiB
ArmAsm
1567 lines
85 KiB
ArmAsm
|
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||
|
|
# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s
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||
|
|
|
||
|
|
vabav.s8 r0, q2, q1
|
||
|
|
vabav.u8 r0, q2, q1
|
||
|
|
vabav.s16 r0, q2, q1
|
||
|
|
vabav.u16 r0, q2, q1
|
||
|
|
vabav.s32 r0, q2, q1
|
||
|
|
vabav.u32 r0, q2, q1
|
||
|
|
vabd.s8 q0, q2, q1
|
||
|
|
vabd.u8 q0, q2, q1
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||
|
|
vabd.s16 q0, q2, q1
|
||
|
|
vabd.u16 q0, q2, q1
|
||
|
|
vabd.s32 q0, q2, q1
|
||
|
|
vabd.u32 q0, q2, q1
|
||
|
|
vabs.s8 q0, q2
|
||
|
|
vabs.s16 q0, q2
|
||
|
|
vabs.s32 q0, q2
|
||
|
|
vadc.i32 q0, q2, q1
|
||
|
|
vadci.i32 q0, q2, q1
|
||
|
|
vadd.i8 q0, q2, q1
|
||
|
|
vadd.i16 q0, q2, q1
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||
|
|
vadd.i32 q0, q2, q1
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||
|
|
vadd.i8 q0, q2, r0
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||
|
|
vadd.i16 q0, q2, r0
|
||
|
|
vadd.i32 q0, q2, r0
|
||
|
|
vaddlv.s32 r0, r1, q1
|
||
|
|
vaddlv.u32 r0, r1, q1
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||
|
|
vaddlva.s32 r0, r1, q1
|
||
|
|
vaddlva.u32 r0, r1, q1
|
||
|
|
vaddv.s8 r0, q1
|
||
|
|
vaddv.u8 r0, q1
|
||
|
|
vaddv.s16 r0, q1
|
||
|
|
vaddv.u16 r0, q1
|
||
|
|
vaddv.s32 r0, q1
|
||
|
|
vaddv.u32 r0, q1
|
||
|
|
vaddva.s8 r0, q1
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||
|
|
vaddva.u8 r0, q1
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||
|
|
vaddva.s16 r0, q1
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||
|
|
vaddva.u16 r0, q1
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||
|
|
vaddva.s32 r0, q1
|
||
|
|
vaddva.u32 r0, q1
|
||
|
|
vand q0, q2, q1
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||
|
|
vbic.i16 q0, #10
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|
|
vbic.i32 q0, #10
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|
|
vbic q0, q2, q1
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||
|
|
vbrsr.8 q0, q2, r0
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|
|
vbrsr.16 q0, q2, r0
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|
|
vbrsr.32 q0, q2, r0
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||
|
|
vcadd.i8 q0, q2, q1, #90
|
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|
|
vcadd.i16 q0, q2, q1, #90
|
||
|
|
vcadd.i32 q0, q2, q1, #90
|
||
|
|
vcls.s8 q0, q2
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||
|
|
vcls.s16 q0, q2
|
||
|
|
vcls.s32 q0, q2
|
||
|
|
vclz.i8 q0, q2
|
||
|
|
vclz.i16 q0, q2
|
||
|
|
vclz.i32 q0, q2
|
||
|
|
vdwdup.u8 q0, r0, r1, #4
|
||
|
|
vdwdup.u16 q0, r0, r1, #4
|
||
|
|
vdwdup.u32 q0, r0, r1, #4
|
||
|
|
vddup.u8 q0, r0, #4
|
||
|
|
vddup.u16 q0, r0, #4
|
||
|
|
vddup.u32 q0, r0, #4
|
||
|
|
vdup.8 q0, r0
|
||
|
|
vdup.16 q0, r0
|
||
|
|
vdup.32 q0, r0
|
||
|
|
veor q0, q2, q1
|
||
|
|
vhadd.s8 q0, q2, q1
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||
|
|
vhadd.u8 q0, q2, q1
|
||
|
|
vhadd.s16 q0, q2, q1
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||
|
|
vhadd.u16 q0, q2, q1
|
||
|
|
vhadd.s32 q0, q2, q1
|
||
|
|
vhadd.u32 q0, q2, q1
|
||
|
|
vhadd.s8 q0, q2, r0
|
||
|
|
vhadd.u8 q0, q2, r0
|
||
|
|
vhadd.s16 q0, q2, r0
|
||
|
|
vhadd.u16 q0, q2, r0
|
||
|
|
vhadd.s32 q0, q2, r0
|
||
|
|
vhadd.u32 q0, q2, r0
|
||
|
|
vhcadd.s8 q0, q2, q1, #90
|
||
|
|
vhcadd.s16 q0, q2, q1, #90
|
||
|
|
vhcadd.s32 q0, q2, q1, #90
|
||
|
|
vhsub.s8 q0, q2, q1
|
||
|
|
vhsub.u8 q0, q2, q1
|
||
|
|
vhsub.s16 q0, q2, q1
|
||
|
|
vhsub.u16 q0, q2, q1
|
||
|
|
vhsub.s32 q0, q2, q1
|
||
|
|
vhsub.u32 q0, q2, q1
|
||
|
|
vhsub.s8 q0, q2, r0
|
||
|
|
vhsub.u8 q0, q2, r0
|
||
|
|
vhsub.s16 q0, q2, r0
|
||
|
|
vhsub.u16 q0, q2, r0
|
||
|
|
vhsub.s32 q0, q2, r0
|
||
|
|
vhsub.u32 q0, q2, r0
|
||
|
|
viwdup.u8 q0, r0, r1, #4
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|
|
viwdup.u16 q0, r0, r1, #4
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||
|
|
viwdup.u32 q0, r0, r1, #4
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||
|
|
vidup.u8 q0, r0, #4
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||
|
|
vidup.u16 q0, r0, #4
|
||
|
|
vidup.u32 q0, r0, #4
|
||
|
|
vmax.s8 q0, q2, q1
|
||
|
|
vmax.u8 q0, q2, q1
|
||
|
|
vmax.s16 q0, q2, q1
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||
|
|
vmax.u16 q0, q2, q1
|
||
|
|
vmax.s32 q0, q2, q1
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||
|
|
vmax.u32 q0, q2, q1
|
||
|
|
vmaxa.s8 q0, q2
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||
|
|
vmaxa.s16 q0, q2
|
||
|
|
vmaxa.s32 q0, q2
|
||
|
|
vmaxv.s8 r0, q2
|
||
|
|
vmaxv.u8 r0, q2
|
||
|
|
vmaxv.s16 r0, q2
|
||
|
|
vmaxv.u16 r0, q2
|
||
|
|
vmaxv.s32 r0, q2
|
||
|
|
vmaxv.u32 r0, q2
|
||
|
|
vmaxav.s8 r0, q2
|
||
|
|
vmaxav.s16 r0, q2
|
||
|
|
vmaxav.s32 r0, q2
|
||
|
|
vmin.s8 q0, q2, q1
|
||
|
|
vmin.u8 q0, q2, q1
|
||
|
|
vmin.s16 q0, q2, q1
|
||
|
|
vmin.u16 q0, q2, q1
|
||
|
|
vmin.s32 q0, q2, q1
|
||
|
|
vmin.u32 q0, q2, q1
|
||
|
|
vmina.s8 q0, q2
|
||
|
|
vmina.s16 q0, q2
|
||
|
|
vmina.s32 q0, q2
|
||
|
|
vminv.s8 r0, q2
|
||
|
|
vminv.u8 r0, q2
|
||
|
|
vminv.s16 r0, q2
|
||
|
|
vminv.u16 r0, q2
|
||
|
|
vminv.s32 r0, q2
|
||
|
|
vminv.u32 r0, q2
|
||
|
|
vminav.s8 r0, q2
|
||
|
|
vminav.s16 r0, q2
|
||
|
|
vminav.s32 r0, q2
|
||
|
|
vmla.i8 q0, q2, r0
|
||
|
|
vmla.i16 q0, q2, r0
|
||
|
|
vmla.i32 q0, q2, r0
|
||
|
|
vmladav.s8 r0, q2, q1
|
||
|
|
vmladav.u8 r0, q2, q1
|
||
|
|
vmladav.s16 r0, q2, q1
|
||
|
|
vmladav.u16 r0, q2, q1
|
||
|
|
vmladav.s32 r0, q2, q1
|
||
|
|
vmladav.u32 r0, q2, q1
|
||
|
|
vmladava.s8 r0, q2, q1
|
||
|
|
vmladava.u8 r0, q2, q1
|
||
|
|
vmladava.s16 r0, q2, q1
|
||
|
|
vmladava.u16 r0, q2, q1
|
||
|
|
vmladava.s32 r0, q2, q1
|
||
|
|
vmladava.u32 r0, q2, q1
|
||
|
|
vmladavax.s8 r0, q2, q1
|
||
|
|
vmladavax.s16 r0, q2, q1
|
||
|
|
vmladavax.s32 r0, q2, q1
|
||
|
|
vmladavx.s8 r0, q2, q1
|
||
|
|
vmladavx.s16 r0, q2, q1
|
||
|
|
vmladavx.s32 r0, q2, q1
|
||
|
|
vmlaldav.s16 r0, r1, q2, q1
|
||
|
|
vmlaldav.u16 r0, r1, q2, q1
|
||
|
|
vmlaldav.s32 r0, r1, q2, q1
|
||
|
|
vmlaldav.u32 r0, r1, q2, q1
|
||
|
|
vmlaldava.s16 r0, r1, q2, q1
|
||
|
|
vmlaldava.u16 r0, r1, q2, q1
|
||
|
|
vmlaldava.s32 r0, r1, q2, q1
|
||
|
|
vmlaldava.u32 r0, r1, q2, q1
|
||
|
|
vmlaldavax.s16 r0, r1, q2, q1
|
||
|
|
vmlaldavax.s32 r0, r1, q2, q1
|
||
|
|
vmlaldavx.s16 r0, r1, q2, q1
|
||
|
|
vmlaldavx.s32 r0, r1, q2, q1
|
||
|
|
vmlas.i8 q0, q2, r0
|
||
|
|
vmlas.i16 q0, q2, r0
|
||
|
|
vmlas.i32 q0, q2, r0
|
||
|
|
vmlsdav.s8 r0, q2, q1
|
||
|
|
vmlsdav.s16 r0, q2, q1
|
||
|
|
vmlsdav.s32 r0, q2, q1
|
||
|
|
vmlsdava.s8 r0, q2, q1
|
||
|
|
vmlsdava.s16 r0, q2, q1
|
||
|
|
vmlsdava.s32 r0, q2, q1
|
||
|
|
vmlsdavax.s8 r0, q2, q1
|
||
|
|
vmlsdavax.s16 r0, q2, q1
|
||
|
|
vmlsdavax.s32 r0, q2, q1
|
||
|
|
vmlsdavx.s8 r0, q2, q1
|
||
|
|
vmlsdavx.s16 r0, q2, q1
|
||
|
|
vmlsdavx.s32 r0, q2, q1
|
||
|
|
vmlsldav.s16 r0, r1, q2, q1
|
||
|
|
vmlsldav.s32 r0, r1, q2, q1
|
||
|
|
vmlsldava.s16 r0, r1, q2, q1
|
||
|
|
vmlsldava.s32 r0, r1, q2, q1
|
||
|
|
vmlsldavax.s16 r0, r1, q2, q1
|
||
|
|
vmlsldavax.s32 r0, r1, q2, q1
|
||
|
|
vmlsldavx.s16 r0, r1, q2, q1
|
||
|
|
vmlsldavx.s32 r0, r1, q2, q1
|
||
|
|
vmov.8 q0[1], r0
|
||
|
|
vmov.16 q0[1], r0
|
||
|
|
vmov.32 q0[1], r0
|
||
|
|
vmov.i8 q0, #0
|
||
|
|
vmov.i16 q0, #0
|
||
|
|
vmov.i32 q0, #0
|
||
|
|
vmov.i64 q0, #0
|
||
|
|
vmov.f32 q0, #1.0
|
||
|
|
vmov r1, r2, q0[2], q0[0]
|
||
|
|
vmov q0[2], q0[0], r1, r2
|
||
|
|
vmov.32 r0, q0[1]
|
||
|
|
vmov.s16 r0, q0[1]
|
||
|
|
vmov.u16 r0, q0[1]
|
||
|
|
vmov.s8 r0, q0[1]
|
||
|
|
vmov.u8 r0, q0[1]
|
||
|
|
vmovlb.s8 q0, q1
|
||
|
|
vmovlb.u8 q0, q1
|
||
|
|
vmovlb.s16 q0, q1
|
||
|
|
vmovlb.u16 q0, q1
|
||
|
|
vmovlt.s8 q0, q1
|
||
|
|
vmovlt.u8 q0, q1
|
||
|
|
vmovlt.s16 q0, q1
|
||
|
|
vmovlt.u16 q0, q1
|
||
|
|
vmovnb.i16 q0, q1
|
||
|
|
vmovnb.i32 q0, q1
|
||
|
|
vmovnt.i16 q0, q1
|
||
|
|
vmovnt.i32 q0, q1
|
||
|
|
vmul.i8 q0, q2, q1
|
||
|
|
vmul.i16 q0, q2, q1
|
||
|
|
vmul.i32 q0, q2, q1
|
||
|
|
vmul.i8 q0, q2, r0
|
||
|
|
vmul.i16 q0, q2, r0
|
||
|
|
vmul.i32 q0, q2, r0
|
||
|
|
vmulh.s8 q0, q2, q1
|
||
|
|
vmulh.u8 q0, q2, q1
|
||
|
|
vmulh.s16 q0, q2, q1
|
||
|
|
vmulh.u16 q0, q2, q1
|
||
|
|
vmulh.s32 q0, q2, q1
|
||
|
|
vmulh.u32 q0, q2, q1
|
||
|
|
vrmulh.s8 q0, q2, q1
|
||
|
|
vrmulh.u8 q0, q2, q1
|
||
|
|
vrmulh.s16 q0, q2, q1
|
||
|
|
vrmulh.u16 q0, q2, q1
|
||
|
|
vrmulh.s32 q0, q2, q1
|
||
|
|
vrmulh.u32 q0, q2, q1
|
||
|
|
vmullb.s8 q0, q2, q1
|
||
|
|
vmullb.u8 q0, q2, q1
|
||
|
|
vmullb.s16 q0, q2, q1
|
||
|
|
vmullb.u16 q0, q2, q1
|
||
|
|
vmullb.s32 q0, q2, q1
|
||
|
|
vmullb.u32 q0, q2, q1
|
||
|
|
vmullt.s8 q0, q2, q1
|
||
|
|
vmullt.u8 q0, q2, q1
|
||
|
|
vmullt.s16 q0, q2, q1
|
||
|
|
vmullt.u16 q0, q2, q1
|
||
|
|
vmullt.s32 q0, q2, q1
|
||
|
|
vmullt.u32 q0, q2, q1
|
||
|
|
vmullb.p8 q0, q2, q1
|
||
|
|
vmullb.p16 q0, q2, q1
|
||
|
|
vmullt.p8 q0, q2, q1
|
||
|
|
vmullt.p16 q0, q2, q1
|
||
|
|
vmvn.i16 q0, #10
|
||
|
|
vmvn.i32 q0, #10
|
||
|
|
vmvn q0, q2
|
||
|
|
vneg.s8 q0, q2
|
||
|
|
vneg.s16 q0, q2
|
||
|
|
vneg.s32 q0, q2
|
||
|
|
vorn q0, q2, q1
|
||
|
|
vorr.i16 q0, #10
|
||
|
|
vorr.i32 q0, #10
|
||
|
|
vorr q0, q2, q1
|
||
|
|
vpsel q0, q2, q1
|
||
|
|
vqabs.s8 q0, q2
|
||
|
|
vqabs.s16 q0, q2
|
||
|
|
vqabs.s32 q0, q2
|
||
|
|
vqadd.s8 q0, q2, q1
|
||
|
|
vqadd.u8 q0, q2, q1
|
||
|
|
vqadd.s16 q0, q2, q1
|
||
|
|
vqadd.u16 q0, q2, q1
|
||
|
|
vqadd.s32 q0, q2, q1
|
||
|
|
vqadd.u32 q0, q2, q1
|
||
|
|
vqadd.s8 q0, q2, r0
|
||
|
|
vqadd.u8 q0, q2, r0
|
||
|
|
vqadd.s16 q0, q2, r0
|
||
|
|
vqadd.u16 q0, q2, r0
|
||
|
|
vqadd.s32 q0, q2, r0
|
||
|
|
vqadd.u32 q0, q2, r0
|
||
|
|
vqdmladh.s8 q0, q2, q1
|
||
|
|
vqdmladh.s16 q0, q2, q1
|
||
|
|
vqdmladh.s32 q0, q2, q1
|
||
|
|
vqdmladhx.s8 q0, q2, q1
|
||
|
|
vqdmladhx.s16 q0, q2, q1
|
||
|
|
vqdmladhx.s32 q0, q2, q1
|
||
|
|
vqrdmladh.s8 q0, q2, q1
|
||
|
|
vqrdmladh.s16 q0, q2, q1
|
||
|
|
vqrdmladh.s32 q0, q2, q1
|
||
|
|
vqrdmladhx.s8 q0, q2, q1
|
||
|
|
vqrdmladhx.s16 q0, q2, q1
|
||
|
|
vqrdmladhx.s32 q0, q2, q1
|
||
|
|
vqdmlah.s8 q0, q2, r0
|
||
|
|
vqdmlah.s16 q0, q2, r0
|
||
|
|
vqdmlah.s32 q0, q2, r0
|
||
|
|
vqrdmlah.s8 q0, q2, r0
|
||
|
|
vqrdmlah.s16 q0, q2, r0
|
||
|
|
vqrdmlah.s32 q0, q2, r0
|
||
|
|
vqdmlash.s8 q0, q2, r0
|
||
|
|
vqdmlash.s16 q0, q2, r0
|
||
|
|
vqdmlash.s32 q0, q2, r0
|
||
|
|
vqrdmlash.s8 q0, q2, r0
|
||
|
|
vqrdmlash.s16 q0, q2, r0
|
||
|
|
vqrdmlash.s32 q0, q2, r0
|
||
|
|
vqdmlsdh.s8 q0, q2, q1
|
||
|
|
vqdmlsdh.s16 q0, q2, q1
|
||
|
|
vqdmlsdh.s32 q0, q2, q1
|
||
|
|
vqdmlsdhx.s8 q0, q2, q1
|
||
|
|
vqdmlsdhx.s16 q0, q2, q1
|
||
|
|
vqdmlsdhx.s32 q0, q2, q1
|
||
|
|
vqrdmlsdh.s8 q0, q2, q1
|
||
|
|
vqrdmlsdh.s16 q0, q2, q1
|
||
|
|
vqrdmlsdh.s32 q0, q2, q1
|
||
|
|
vqrdmlsdhx.s8 q0, q2, q1
|
||
|
|
vqrdmlsdhx.s16 q0, q2, q1
|
||
|
|
vqrdmlsdhx.s32 q0, q2, q1
|
||
|
|
vqdmulh.s8 q0, q2, q1
|
||
|
|
vqdmulh.s16 q0, q2, q1
|
||
|
|
vqdmulh.s32 q0, q2, q1
|
||
|
|
vqrdmulh.s8 q0, q2, q1
|
||
|
|
vqrdmulh.s16 q0, q2, q1
|
||
|
|
vqrdmulh.s32 q0, q2, q1
|
||
|
|
vqdmulh.s8 q0, q2, r0
|
||
|
|
vqdmulh.s16 q0, q2, r0
|
||
|
|
vqdmulh.s32 q0, q2, r0
|
||
|
|
vqrdmulh.s8 q0, q2, r0
|
||
|
|
vqrdmulh.s16 q0, q2, r0
|
||
|
|
vqrdmulh.s32 q0, q2, r0
|
||
|
|
vqdmullt.s16 q0, q2, q1
|
||
|
|
vqdmullt.s32 q0, q2, q1
|
||
|
|
vqdmullb.s16 q0, q2, r0
|
||
|
|
vqdmullb.s32 q0, q2, r0
|
||
|
|
vqmovnt.s16 q0, q2
|
||
|
|
vqmovnt.u16 q0, q2
|
||
|
|
vqmovnt.s32 q0, q2
|
||
|
|
vqmovnt.u32 q0, q2
|
||
|
|
vqmovnb.s16 q0, q2
|
||
|
|
vqmovnb.u16 q0, q2
|
||
|
|
vqmovnb.s32 q0, q2
|
||
|
|
vqmovnb.u32 q0, q2
|
||
|
|
vqmovunt.s16 q0, q2
|
||
|
|
vqmovunt.s32 q0, q2
|
||
|
|
vqmovunb.s16 q0, q2
|
||
|
|
vqmovunb.s32 q0, q2
|
||
|
|
vqneg.s8 q0, q2
|
||
|
|
vqneg.s16 q0, q2
|
||
|
|
vqneg.s32 q0, q2
|
||
|
|
vqrshl.s8 q0, q2, q1
|
||
|
|
vqrshl.u8 q0, q2, q1
|
||
|
|
vqrshl.s16 q0, q2, q1
|
||
|
|
vqrshl.u16 q0, q2, q1
|
||
|
|
vqrshl.s32 q0, q2, q1
|
||
|
|
vqrshl.u32 q0, q2, q1
|
||
|
|
vqrshl.s8 q0, r0
|
||
|
|
vqrshl.u8 q0, r0
|
||
|
|
vqrshl.s16 q0, r0
|
||
|
|
vqrshl.u16 q0, r0
|
||
|
|
vqrshl.s32 q0, r0
|
||
|
|
vqrshl.u32 q0, r0
|
||
|
|
vqrshrnb.s16 q0, q2, #5
|
||
|
|
vqrshrnb.u16 q0, q2, #5
|
||
|
|
vqrshrnb.s32 q0, q2, #5
|
||
|
|
vqrshrnb.u32 q0, q2, #5
|
||
|
|
vqrshrnt.s16 q0, q2, #5
|
||
|
|
vqrshrnt.u16 q0, q2, #5
|
||
|
|
vqrshrnt.s32 q0, q2, #5
|
||
|
|
vqrshrnt.u32 q0, q2, #5
|
||
|
|
vqrshrunb.s16 q0, q2, #5
|
||
|
|
vqrshrunb.s32 q0, q2, #5
|
||
|
|
vqrshrunt.s16 q0, q2, #5
|
||
|
|
vqrshrunt.s32 q0, q2, #5
|
||
|
|
vqshl.s8 q0, r0
|
||
|
|
vqshl.u8 q0, r0
|
||
|
|
vqshl.s16 q0, r0
|
||
|
|
vqshl.u16 q0, r0
|
||
|
|
vqshl.s32 q0, r0
|
||
|
|
vqshl.u32 q0, r0
|
||
|
|
vqshl.s8 q0, q2, #5
|
||
|
|
vqshl.u8 q0, q2, #5
|
||
|
|
vqshl.s16 q0, q2, #5
|
||
|
|
vqshl.u16 q0, q2, #5
|
||
|
|
vqshl.s32 q0, q2, #5
|
||
|
|
vqshl.u32 q0, q2, #5
|
||
|
|
vqshlu.s8 q0, q2, #5
|
||
|
|
vqshlu.s16 q0, q2, #5
|
||
|
|
vqshlu.s32 q0, q2, #5
|
||
|
|
vqshl.s8 q0, q2, q1
|
||
|
|
vqshl.u8 q0, q2, q1
|
||
|
|
vqshl.s16 q0, q2, q1
|
||
|
|
vqshl.u16 q0, q2, q1
|
||
|
|
vqshl.s32 q0, q2, q1
|
||
|
|
vqshl.u32 q0, q2, q1
|
||
|
|
vqshrnb.s16 q0, q2, #5
|
||
|
|
vqshrnb.u16 q0, q2, #5
|
||
|
|
vqshrnb.s32 q0, q2, #5
|
||
|
|
vqshrnb.u32 q0, q2, #5
|
||
|
|
vqshrnt.s16 q0, q2, #5
|
||
|
|
vqshrnt.u16 q0, q2, #5
|
||
|
|
vqshrnt.s32 q0, q2, #5
|
||
|
|
vqshrnt.u32 q0, q2, #5
|
||
|
|
vqshrunb.s16 q0, q2, #5
|
||
|
|
vqshrunb.s32 q0, q2, #5
|
||
|
|
vqshrunt.s16 q0, q2, #5
|
||
|
|
vqshrunt.s32 q0, q2, #5
|
||
|
|
vqsub.s8 q0, q2, q1
|
||
|
|
vqsub.u8 q0, q2, q1
|
||
|
|
vqsub.s16 q0, q2, q1
|
||
|
|
vqsub.u16 q0, q2, q1
|
||
|
|
vqsub.s32 q0, q2, q1
|
||
|
|
vqsub.u32 q0, q2, q1
|
||
|
|
vqsub.s8 q0, q2, r0
|
||
|
|
vqsub.u8 q0, q2, r0
|
||
|
|
vqsub.s16 q0, q2, r0
|
||
|
|
vqsub.u16 q0, q2, r0
|
||
|
|
vqsub.s32 q0, q2, r0
|
||
|
|
vqsub.u32 q0, q2, r0
|
||
|
|
vrev16.8 q0, q2
|
||
|
|
vrev32.8 q0, q2
|
||
|
|
vrev32.16 q0, q2
|
||
|
|
vrev64.8 q0, q2
|
||
|
|
vrev64.16 q0, q2
|
||
|
|
vrev64.32 q0, q2
|
||
|
|
vrhadd.s8 q0, q2, q1
|
||
|
|
vrhadd.u8 q0, q2, q1
|
||
|
|
vrhadd.s16 q0, q2, q1
|
||
|
|
vrhadd.u16 q0, q2, q1
|
||
|
|
vrhadd.s32 q0, q2, q1
|
||
|
|
vrhadd.u32 q0, q2, q1
|
||
|
|
vrmlaldavh.s32 r0, r1, q2, q1
|
||
|
|
vrmlaldavh.u32 r0, r1, q2, q1
|
||
|
|
vrmlaldavha.s32 r0, r1, q2, q1
|
||
|
|
vrmlaldavha.u32 r0, r1, q2, q1
|
||
|
|
vrmlaldavhx.s32 r0, r1, q2, q1
|
||
|
|
vrmlaldavhax.s32 r0, r1, q2, q1
|
||
|
|
vrmlsldavh.s32 r0, r1, q2, q1
|
||
|
|
vrmlsldavha.s32 r0, r1, q2, q1
|
||
|
|
vrmlsldavhx.s32 r0, r1, q2, q1
|
||
|
|
vrmlsldavhax.s32 r0, r1, q2, q1
|
||
|
|
vrshl.s8 q0, q2, q1
|
||
|
|
vrshl.u8 q0, q2, q1
|
||
|
|
vrshl.s16 q0, q2, q1
|
||
|
|
vrshl.u16 q0, q2, q1
|
||
|
|
vrshl.s32 q0, q2, q1
|
||
|
|
vrshl.u32 q0, q2, q1
|
||
|
|
vrshl.s8 q0, r0
|
||
|
|
vrshl.u8 q0, r0
|
||
|
|
vrshl.s16 q0, r0
|
||
|
|
vrshl.u16 q0, r0
|
||
|
|
vrshl.s32 q0, r0
|
||
|
|
vrshl.u32 q0, r0
|
||
|
|
vrshr.s8 q0, q2, #5
|
||
|
|
vrshr.u8 q0, q2, #5
|
||
|
|
vrshr.s16 q0, q2, #5
|
||
|
|
vrshr.u16 q0, q2, #5
|
||
|
|
vrshr.s32 q0, q2, #5
|
||
|
|
vrshr.u32 q0, q2, #5
|
||
|
|
vrshrnb.i16 q0, q2, #5
|
||
|
|
vrshrnb.i32 q0, q2, #5
|
||
|
|
vrshrnt.i16 q0, q2, #5
|
||
|
|
vrshrnt.i32 q0, q2, #5
|
||
|
|
vsbc.i32 q0, q2, q1
|
||
|
|
vsbci.i32 q0, q2, q1
|
||
|
|
vshl.i8 q0, q2, #1
|
||
|
|
vshl.i16 q0, q2, #1
|
||
|
|
vshl.i32 q0, q2, #1
|
||
|
|
vshl.s8 q0, r0
|
||
|
|
vshl.u8 q0, r0
|
||
|
|
vshl.s16 q0, r0
|
||
|
|
vshl.u16 q0, r0
|
||
|
|
vshl.s32 q0, r0
|
||
|
|
vshl.u32 q0, r0
|
||
|
|
vshl.s8 q0, q2, q1
|
||
|
|
vshl.u8 q0, q2, q1
|
||
|
|
vshl.s16 q0, q2, q1
|
||
|
|
vshl.u16 q0, q2, q1
|
||
|
|
vshl.s32 q0, q2, q1
|
||
|
|
vshl.u32 q0, q2, q1
|
||
|
|
vshlc q0, r0, #5
|
||
|
|
vshllt.s8 q0, q2, #5
|
||
|
|
vshllt.u8 q0, q2, #5
|
||
|
|
vshllt.s16 q0, q2, #5
|
||
|
|
vshllt.u16 q0, q2, #5
|
||
|
|
vshllb.s8 q0, q2, #5
|
||
|
|
vshllb.u8 q0, q2, #5
|
||
|
|
vshllb.s16 q0, q2, #5
|
||
|
|
vshllb.u16 q0, q2, #5
|
||
|
|
vshllt.s8 q0, q2, #8
|
||
|
|
vshllt.u8 q0, q2, #8
|
||
|
|
vshllt.s16 q0, q2, #16
|
||
|
|
vshllt.u16 q0, q2, #16
|
||
|
|
vshllb.s8 q0, q2, #8
|
||
|
|
vshllb.u8 q0, q2, #8
|
||
|
|
vshllb.s16 q0, q2, #16
|
||
|
|
vshllb.u16 q0, q2, #16
|
||
|
|
vshr.s8 q0, q2, #5
|
||
|
|
vshr.u8 q0, q2, #5
|
||
|
|
vshr.s16 q0, q2, #5
|
||
|
|
vshr.u16 q0, q2, #5
|
||
|
|
vshr.s32 q0, q2, #5
|
||
|
|
vshr.u32 q0, q2, #5
|
||
|
|
vshrnb.i16 q0, q2, #5
|
||
|
|
vshrnb.i32 q0, q2, #5
|
||
|
|
vshrnt.i16 q0, q2, #5
|
||
|
|
vshrnt.i32 q0, q2, #5
|
||
|
|
vsli.8 q0, q2, #5
|
||
|
|
vsli.16 q0, q2, #5
|
||
|
|
vsli.32 q0, q2, #5
|
||
|
|
vsri.8 q0, q2, #5
|
||
|
|
vsri.16 q0, q2, #5
|
||
|
|
vsri.32 q0, q2, #5
|
||
|
|
vsub.i8 q0, q2, q1
|
||
|
|
vsub.i16 q0, q2, q1
|
||
|
|
vsub.i32 q0, q2, q1
|
||
|
|
vsub.i8 q0, q2, r0
|
||
|
|
vsub.i16 q0, q2, r0
|
||
|
|
vsub.i32 q0, q2, r0
|
||
|
|
|
||
|
|
# CHECK: Instruction Info:
|
||
|
|
# CHECK-NEXT: [1]: #uOps
|
||
|
|
# CHECK-NEXT: [2]: Latency
|
||
|
|
# CHECK-NEXT: [3]: RThroughput
|
||
|
|
# CHECK-NEXT: [4]: MayLoad
|
||
|
|
# CHECK-NEXT: [5]: MayStore
|
||
|
|
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||
|
|
|
||
|
|
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vabav.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vabav.u8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vabav.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vabav.u16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vabav.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vabav.u32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabs.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabs.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vabs.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 U vadc.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 U vadci.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vadd.i8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vadd.i16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vadd.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vadd.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vadd.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vadd.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddlv.s32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddlv.u32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddlva.s32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddlva.u32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddv.s8 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddv.u8 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddv.s16 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddv.u16 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddv.s32 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddv.u32 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddva.s8 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddva.u8 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddva.s16 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddva.u16 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddva.s32 r0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vaddva.u32 r0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vand q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vbic.i16 q0, #0xa
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vbic.i32 q0, #0xa
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vbic q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vbrsr.8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vbrsr.16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vbrsr.32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vcadd.i8 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vcadd.i16 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vcadd.i32 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vcls.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vcls.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vcls.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vclz.i8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vclz.i16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vclz.i32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vdwdup.u8 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vdwdup.u16 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vdwdup.u32 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vddup.u8 q0, r0, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vddup.u16 q0, r0, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vddup.u32 q0, r0, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vdup.8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vdup.16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vdup.32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 veor q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhadd.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhcadd.s8 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhcadd.s16 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhcadd.s32 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vhsub.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 viwdup.u8 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 viwdup.u16 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 viwdup.u32 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vidup.u8 q0, r0, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vidup.u16 q0, r0, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vidup.u32 q0, r0, #4
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmax.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmax.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmax.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmax.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmax.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmax.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmaxa.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmaxa.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmaxa.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 4 2.00 vmaxv.s8 r0, q2
|
||
|
|
# CHECK-NEXT: 1 4 2.00 vmaxv.u8 r0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmaxv.s16 r0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmaxv.u16 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmaxv.s32 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmaxv.u32 r0, q2
|
||
|
|
# CHECK-NEXT: 1 4 2.00 vmaxav.s8 r0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmaxav.s16 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmaxav.s32 r0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmin.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmin.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmin.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmin.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmin.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmin.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmina.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmina.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmina.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 4 2.00 vminv.s8 r0, q2
|
||
|
|
# CHECK-NEXT: 1 4 2.00 vminv.u8 r0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vminv.s16 r0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vminv.u16 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vminv.s32 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vminv.u32 r0, q2
|
||
|
|
# CHECK-NEXT: 1 4 2.00 vminav.s8 r0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vminav.s16 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vminav.s32 r0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmla.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmla.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmla.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlav.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlav.u8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlav.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlav.u16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlav.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlav.u32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlava.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlava.u8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlava.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlava.u16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlava.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlava.u32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmladavax.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmladavax.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmladavax.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmladavx.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmladavx.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmladavx.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalv.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalv.u16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalv.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalv.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalva.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalva.u16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalva.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlalva.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlaldavax.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlaldavax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlaldavx.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlaldavx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlas.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlas.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlas.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdav.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdav.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdav.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdava.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdava.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdava.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdavax.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdavax.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdavax.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdavx.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdavx.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsdavx.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldav.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldav.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldava.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldava.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldavax.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldavax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldavx.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmlsldavx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 1.00 vmov.8 q0[1], r0
|
||
|
|
# CHECK-NEXT: 1 1 1.00 vmov.16 q0[1], r0
|
||
|
|
# CHECK-NEXT: 1 1 1.00 vmov.32 q0[1], r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmov.i8 q0, #0x0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmov.i16 q0, #0x0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmov.i32 q0, #0x0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmov.i64 q0, #0x0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmov.f32 q0, #1.000000e+00
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmov r1, r2, q0[2], q0[0]
|
||
|
|
# CHECK-NEXT: 1 1 1.00 vmov q0[2], q0[0], r1, r2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmov.32 r0, q0[1]
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmov.s16 r0, q0[1]
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmov.u16 r0, q0[1]
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmov.s8 r0, q0[1]
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmov.u8 r0, q0[1]
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlb.s8 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlb.u8 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlb.s16 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlb.u16 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlt.s8 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlt.u8 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlt.s16 q0, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmovlt.u16 q0, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmovnb.i16 q0, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmovnb.i32 q0, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmovnt.i16 q0, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vmovnt.i32 q0, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmul.i8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmul.i16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmul.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmul.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmul.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmul.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmulh.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmulh.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmulh.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmulh.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmulh.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmulh.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.p8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullb.p16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.p8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vmullt.p16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmvn.i16 q0, #0xa
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmvn.i32 q0, #0xa
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vmvn q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vneg.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vneg.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vneg.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vorn q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vorr.i16 q0, #0xa
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vorr.i32 q0, #0xa
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vorr q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vpsel q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqabs.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqabs.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqabs.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqadd.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmladh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmladh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmladh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmladhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmladhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmladhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmladh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmladh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmladh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmladhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmladhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmladhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlah.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlah.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlah.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlah.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlah.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlah.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlash.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlash.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlash.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlash.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlash.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlash.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlsdh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlsdh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlsdh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlsdhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlsdhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmlsdhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlsdh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlsdh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlsdh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlsdhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlsdhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmlsdhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmulh.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmulh.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmulh.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmulh.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmulh.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrdmulh.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmullt.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmullt.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmullb.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqdmullb.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnt.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnt.u16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnt.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnt.u32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnb.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnb.u16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnb.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovnb.u32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovunt.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovunt.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovunb.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqmovunb.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqneg.s8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqneg.s16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqneg.s32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqrshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnb.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnb.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnt.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrnt.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrunb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrunb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrunt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqrshrunt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshlu.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshlu.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshlu.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vqshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnb.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnb.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnt.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrnt.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrunb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrunb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrunt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vqshrunt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vqsub.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrev16.8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrev32.8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrev32.16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrev64.8 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrev64.16 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrev64.32 q0, q2
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrhadd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrhadd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrhadd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrhadd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrhadd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vrhadd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlalvh.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlalvh.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlalvha.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlalvha.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlaldavhx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlaldavhax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlsldavh.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlsldavha.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlsldavhx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrmlsldavhax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshr.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshr.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshr.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshr.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshr.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 vrshr.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vrshrnb.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vrshrnb.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vrshrnt.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vrshrnt.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 2 2.00 U vsbc.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 2 2.00 U vsbci.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.i8 q0, q2, #1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.i16 q0, q2, #1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.i32 q0, q2, #1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 U vshlc q0, r0, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.s8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.u8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.s16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllt.u16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.s8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.u8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.s16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshllb.u16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshr.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshr.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshr.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshr.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshr.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vshr.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vshrnb.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vshrnb.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vshrnt.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 3 2.00 vshrnt.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsli.8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsli.16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsli.32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsri.8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsri.16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsri.32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsub.i8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsub.i16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsub.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsub.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsub.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: 1 1 2.00 vsub.i32 q0, q2, r0
|
||
|
|
|
||
|
|
# CHECK: Resources:
|
||
|
|
# CHECK-NEXT: [0] - M55UnitALU
|
||
|
|
# CHECK-NEXT: [1] - M55UnitLoadStore
|
||
|
|
# CHECK-NEXT: [2] - M55UnitVecALU
|
||
|
|
# CHECK-NEXT: [3] - M55UnitVecFPALU
|
||
|
|
# CHECK-NEXT: [4] - M55UnitVecSys
|
||
|
|
|
||
|
|
# CHECK: Resource pressure per iteration:
|
||
|
|
# CHECK-NEXT: [0] [1] [2] [3] [4]
|
||
|
|
# CHECK-NEXT: - - 672.00 354.00 -
|
||
|
|
|
||
|
|
# CHECK: Resource pressure by instruction:
|
||
|
|
# CHECK-NEXT: [0] [1] [2] [3] [4] Instructions:
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabav.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabav.u8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabav.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabav.u16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabav.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabav.u32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabs.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabs.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vabs.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadc.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadci.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadd.i8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadd.i16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadd.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadd.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadd.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vadd.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddlv.s32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddlv.u32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddlva.s32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddlva.u32 r0, r1, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddv.s8 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddv.u8 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddv.s16 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddv.u16 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddv.s32 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddv.u32 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddva.s8 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddva.u8 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddva.s16 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddva.u16 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddva.s32 r0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vaddva.u32 r0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vand q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vbic.i16 q0, #0xa
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vbic.i32 q0, #0xa
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vbic q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vbrsr.8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vbrsr.16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vbrsr.32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vcadd.i8 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vcadd.i16 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vcadd.i32 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vcls.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vcls.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vcls.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vclz.i8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vclz.i16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vclz.i32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vdwdup.u8 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vdwdup.u16 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vdwdup.u32 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vddup.u8 q0, r0, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vddup.u16 q0, r0, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vddup.u32 q0, r0, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vdup.8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vdup.16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vdup.32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - veor q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhadd.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhcadd.s8 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhcadd.s16 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhcadd.s32 q0, q2, q1, #90
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vhsub.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - viwdup.u8 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - viwdup.u16 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - viwdup.u32 q0, r0, r1, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vidup.u8 q0, r0, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vidup.u16 q0, r0, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vidup.u32 q0, r0, #4
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmax.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmax.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmax.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmax.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmax.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmax.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxa.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxa.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxa.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxv.s8 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxv.u8 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxv.s16 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxv.u16 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxv.s32 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxv.u32 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxav.s8 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxav.s16 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmaxav.s32 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmin.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmin.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmin.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmin.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmin.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmin.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmina.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmina.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmina.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminv.s8 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminv.u8 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminv.s16 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminv.u16 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminv.s32 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminv.u32 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminav.s8 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminav.s16 r0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vminav.s32 r0, q2
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmla.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmla.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmla.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlav.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlav.u8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlav.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlav.u16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlav.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlav.u32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlava.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlava.u8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlava.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlava.u16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlava.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlava.u32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmladavax.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmladavax.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmladavax.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmladavx.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmladavx.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmladavx.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalv.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalv.u16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalv.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalv.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalva.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalva.u16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalva.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlalva.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlaldavax.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlaldavax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlaldavx.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlaldavx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlas.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlas.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlas.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdav.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdav.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdav.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdava.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdava.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdava.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdavax.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdavax.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdavax.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdavx.s8 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdavx.s16 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsdavx.s32 r0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldav.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldav.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldava.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldava.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldavax.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldavax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldavx.s16 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmlsldavx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - 1.00 1.00 - vmov.8 q0[1], r0
|
||
|
|
# CHECK-NEXT: - - 1.00 1.00 - vmov.16 q0[1], r0
|
||
|
|
# CHECK-NEXT: - - 1.00 1.00 - vmov.32 q0[1], r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.i8 q0, #0x0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.i16 q0, #0x0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.i32 q0, #0x0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.i64 q0, #0x0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.f32 q0, #1.000000e+00
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov r1, r2, q0[2], q0[0]
|
||
|
|
# CHECK-NEXT: - - 1.00 1.00 - vmov q0[2], q0[0], r1, r2
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.32 r0, q0[1]
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.s16 r0, q0[1]
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.u16 r0, q0[1]
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.s8 r0, q0[1]
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmov.u8 r0, q0[1]
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlb.s8 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlb.u8 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlb.s16 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlb.u16 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlt.s8 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlt.u8 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlt.s16 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovlt.u16 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovnb.i16 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovnb.i32 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovnt.i16 q0, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmovnt.i32 q0, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmul.i8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmul.i16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmul.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmul.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmul.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmul.i32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmulh.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmulh.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmulh.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmulh.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmulh.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmulh.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullb.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullb.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullb.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullb.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullb.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullb.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullt.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullt.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullt.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullt.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullt.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vmullt.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmullb.p8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmullb.p16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmullt.p8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmullt.p16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmvn.i16 q0, #0xa
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmvn.i32 q0, #0xa
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vmvn q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vneg.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vneg.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vneg.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vorn q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vorr.i16 q0, #0xa
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vorr.i32 q0, #0xa
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vorr q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vpsel q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqabs.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqabs.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqabs.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqadd.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmladh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmladh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmladh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmladhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmladhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmladhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmladh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmladh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmladh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmladhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmladhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmladhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlah.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlah.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlah.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlah.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlah.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlah.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlash.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlash.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlash.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlash.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlash.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlash.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlsdh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlsdh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlsdh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlsdhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlsdhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmlsdhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlsdh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlsdh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlsdh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlsdhx.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlsdhx.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmlsdhx.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmulh.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmulh.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmulh.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmulh.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmulh.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmulh.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmulh.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmulh.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqrdmulh.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmullt.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmullt.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmullb.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vqdmullb.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnt.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnt.u16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnt.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnt.u32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnb.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnb.u16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnb.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovnb.u32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovunt.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovunt.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovunb.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqmovunb.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqneg.s8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqneg.s16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqneg.s32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnb.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnb.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnt.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrnt.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrunb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrunb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrunt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqrshrunt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshlu.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshlu.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshlu.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnb.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnb.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnt.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrnt.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrunb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrunb.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrunt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqshrunt.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.s8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.u8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.s16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.u16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.s32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vqsub.u32 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrev16.8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrev32.8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrev32.16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrev64.8 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrev64.16 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrev64.32 q0, q2
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrhadd.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrhadd.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrhadd.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrhadd.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrhadd.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrhadd.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlalvh.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlalvh.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlalvha.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlalvha.u32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlaldavhx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlaldavhax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlsldavh.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlsldavha.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlsldavhx.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - - 2.00 - vrmlsldavhax.s32 r0, r1, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshr.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshr.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshr.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshr.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshr.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshr.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshrnb.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshrnb.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshrnt.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vrshrnt.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsbc.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsbci.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.i8 q0, q2, #1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.i16 q0, q2, #1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.i32 q0, q2, #1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.s8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.u8 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.s16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.u16 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.s32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.u32 q0, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.s8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.u8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.s16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.u16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.s32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshl.u32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshlc q0, r0, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.s8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.u8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.s16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllt.u16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.s8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.u8 q0, q2, #8
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.s16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshllb.u16 q0, q2, #16
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshr.s8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshr.u8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshr.s16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshr.u16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshr.s32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshr.u32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshrnb.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshrnb.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshrnt.i16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vshrnt.i32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsli.8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsli.16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsli.32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsri.8 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsri.16 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsri.32 q0, q2, #5
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsub.i8 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsub.i16 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsub.i32 q0, q2, q1
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsub.i8 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsub.i16 q0, q2, r0
|
||
|
|
# CHECK-NEXT: - - 2.00 - - vsub.i32 q0, q2, r0
|