42 lines
1.7 KiB
ArmAsm
42 lines
1.7 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids -instruction-tables < %s | FileCheck %s
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prefetch (%rax)
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prefetchw (%rax)
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 5 0.33 * * prefetch (%rax)
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# CHECK-NEXT: 1 5 0.33 * * prefetchw (%rax)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SPRPort00
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# CHECK-NEXT: [1] - SPRPort01
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# CHECK-NEXT: [2] - SPRPort02
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# CHECK-NEXT: [3] - SPRPort03
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# CHECK-NEXT: [4] - SPRPort04
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# CHECK-NEXT: [5] - SPRPort05
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# CHECK-NEXT: [6] - SPRPort06
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# CHECK-NEXT: [7] - SPRPort07
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# CHECK-NEXT: [8] - SPRPort08
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# CHECK-NEXT: [9] - SPRPort09
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# CHECK-NEXT: [10] - SPRPort10
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# CHECK-NEXT: [11] - SPRPort11
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# CHECK-NEXT: [12] - SPRPortInvalid
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
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# CHECK-NEXT: - - 0.67 0.67 - - - - - - - 0.67 -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
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# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetch (%rax)
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# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetchw (%rax)
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