425 lines
19 KiB
C++
425 lines
19 KiB
C++
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//===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate ROCDLIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h"
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#include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
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#include "mlir/Dialect/Arith/Transforms/Passes.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Pass/PassManager.h"
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#include "mlir/Transforms/Passes.h"
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#include "mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h"
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#include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h"
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#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h"
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#include "mlir/Conversion/GPUCommon/GPUCommonPass.h"
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#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
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#include "mlir/Conversion/LLVMCommon/LoweringOptions.h"
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#include "mlir/Conversion/LLVMCommon/Pattern.h"
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#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
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#include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h"
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#include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
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#include "mlir/Dialect/ControlFlow/IR/ControlFlow.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/GPU/Transforms/Passes.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
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#include "mlir/Dialect/Math/IR/Math.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/Vector/IR/VectorOps.h"
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#include "mlir/IR/BuiltinAttributes.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "../GPUCommon/GPUOpsLowering.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTGPUOPSTOROCDLOPS
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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/// Returns true if the given `gpu.func` can be safely called using the bare
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/// pointer calling convention.
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static bool canBeCalledWithBarePointers(gpu::GPUFuncOp func) {
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bool canBeBare = true;
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for (Type type : func.getArgumentTypes())
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if (auto memrefTy = dyn_cast<BaseMemRefType>(type))
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canBeBare &= LLVMTypeConverter::canConvertToBarePtr(memrefTy);
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return canBeBare;
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}
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Value getLaneId(ConversionPatternRewriter &rewriter, Location loc,
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const unsigned indexBitwidth) {
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auto int32Type = IntegerType::get(rewriter.getContext(), 32);
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Value zero = rewriter.createOrFold<arith::ConstantIntOp>(loc, 0, 32);
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Value minus1 = rewriter.createOrFold<arith::ConstantIntOp>(loc, -1, 32);
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Value mbcntLo = rewriter.create<ROCDL::MbcntLoOp>(loc, int32Type,
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ValueRange{minus1, zero});
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Value laneId = rewriter.create<ROCDL::MbcntHiOp>(loc, int32Type,
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ValueRange{minus1, mbcntLo});
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return laneId;
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}
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namespace {
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struct GPULaneIdOpToROCDL : ConvertOpToLLVMPattern<gpu::LaneIdOp> {
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using ConvertOpToLLVMPattern<gpu::LaneIdOp>::ConvertOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(gpu::LaneIdOp op, gpu::LaneIdOp::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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auto loc = op->getLoc();
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MLIRContext *context = rewriter.getContext();
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// convert to: %mlo = call @llvm.amdgcn.mbcnt.lo(-1, 0)
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// followed by: %lid = call @llvm.amdgcn.mbcnt.hi(-1, %mlo)
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Type intTy = IntegerType::get(context, 32);
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Value zero = rewriter.createOrFold<arith::ConstantIntOp>(loc, 0, 32);
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Value minus1 = rewriter.createOrFold<arith::ConstantIntOp>(loc, -1, 32);
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Value mbcntLo =
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rewriter.create<ROCDL::MbcntLoOp>(loc, intTy, ValueRange{minus1, zero});
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Value laneId = rewriter.create<ROCDL::MbcntHiOp>(
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loc, intTy, ValueRange{minus1, mbcntLo});
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// Truncate or extend the result depending on the index bitwidth specified
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// by the LLVMTypeConverter options.
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const unsigned indexBitwidth = getTypeConverter()->getIndexTypeBitwidth();
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if (indexBitwidth > 32) {
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laneId = rewriter.create<LLVM::SExtOp>(
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loc, IntegerType::get(context, indexBitwidth), laneId);
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} else if (indexBitwidth < 32) {
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laneId = rewriter.create<LLVM::TruncOp>(
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loc, IntegerType::get(context, indexBitwidth), laneId);
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}
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rewriter.replaceOp(op, {laneId});
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return success();
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}
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};
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struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> {
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using ConvertOpToLLVMPattern<gpu::ShuffleOp>::ConvertOpToLLVMPattern;
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/// Lowers a shuffle to the corresponding ROCDL ops.
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///
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/// Use the `width` argument to see if src lane is participating.
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/// If not the dstLane would be itself.
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///
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/// Shuffle with DS Bpermute:
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/// let shflMode = [xor, up, down, idx]
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/// let width = 32(usually warpsize), step = [1, 2, 4, 8, 16, ... , width].
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/// 1. curLaneId = using mbcnt.lo + mbcnt.hi
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/// 2. widthOrZeroIfOutside = (curLaneId + width) & -width
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/// 3. dstLane = shflMode(curLaneId, step)
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/// 4. isActiveSrcLane = dstLane < isActiveSrcLane
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/// 5. dstLane = isActiveSrcLane ? dstLane : curLaneId
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/// 6. dwordAlignedDstLane = dstLane * 4 or dstLane << 2.
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/// 7. bpermute(dwordAlignedDstLane, shfl_value).
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///
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LogicalResult
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matchAndRewrite(gpu::ShuffleOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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// TODO: Add support for non 32-bit shuffle values.
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if (adaptor.getValue().getType().getIntOrFloatBitWidth() != 32)
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return failure();
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const unsigned indexBitwidth = getTypeConverter()->getIndexTypeBitwidth();
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Value srcLaneId = getLaneId(rewriter, loc, indexBitwidth);
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auto int32Type = IntegerType::get(rewriter.getContext(), 32);
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Value width = adaptor.getWidth();
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Value zero = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 0);
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Value negwidth = rewriter.create<LLVM::SubOp>(loc, int32Type, zero, width);
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Value add = rewriter.create<LLVM::AddOp>(loc, int32Type, srcLaneId, width);
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Value widthOrZeroIfOutside =
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rewriter.create<LLVM::AndOp>(loc, int32Type, add, negwidth);
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Value dstLane;
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// TODO: Add support for gpu::ShuffleMode::UP and gpu::ShuffleMode::DOWN.
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// TODO: Use ds_swizzle for XOR when step/offsets are constants for better
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// perf.
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switch (op.getMode()) {
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case gpu::ShuffleMode::XOR:
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dstLane = rewriter.create<LLVM::XOrOp>(loc, int32Type, srcLaneId,
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adaptor.getOffset());
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break;
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case gpu::ShuffleMode::IDX:
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dstLane = adaptor.getOffset();
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break;
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default:
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return failure();
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}
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Value isActiveSrcLane = rewriter.create<LLVM::ICmpOp>(
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loc, LLVM::ICmpPredicate::slt, dstLane, widthOrZeroIfOutside);
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Value selectDstLane = rewriter.create<LLVM::SelectOp>(loc, isActiveSrcLane,
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dstLane, srcLaneId);
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Value two = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 2);
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Value dwordAlignedDstLane =
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rewriter.create<LLVM::ShlOp>(loc, int32Type, selectDstLane, two);
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Value initShflValue = adaptor.getValue();
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if (adaptor.getValue().getType().isF32()) {
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initShflValue =
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rewriter.create<LLVM::BitcastOp>(loc, int32Type, initShflValue);
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}
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Value shflValue = rewriter.create<ROCDL::DsBpermuteOp>(
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loc, int32Type, dwordAlignedDstLane, initShflValue);
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if (adaptor.getValue().getType().isF32()) {
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shflValue = rewriter.create<LLVM::BitcastOp>(
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loc, adaptor.getValue().getType(), shflValue);
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}
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rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
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return success();
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}
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};
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/// Import the GPU Ops to ROCDL Patterns.
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#include "GPUToROCDL.cpp.inc"
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// A pass that replaces all occurrences of GPU device operations with their
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// corresponding ROCDL equivalent.
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//
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// This pass only handles device code and is not meant to be run on GPU host
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// code.
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struct LowerGpuOpsToROCDLOpsPass
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: public impl::ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> {
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LowerGpuOpsToROCDLOpsPass() = default;
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LowerGpuOpsToROCDLOpsPass(const std::string &chipset, unsigned indexBitwidth,
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bool useBarePtrCallConv,
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gpu::amd::Runtime runtime) {
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if (this->chipset.getNumOccurrences() == 0)
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this->chipset = chipset;
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if (this->indexBitwidth.getNumOccurrences() == 0)
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this->indexBitwidth = indexBitwidth;
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if (this->useBarePtrCallConv.getNumOccurrences() == 0)
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this->useBarePtrCallConv = useBarePtrCallConv;
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if (this->runtime.getNumOccurrences() == 0)
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this->runtime = runtime;
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}
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void runOnOperation() override {
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gpu::GPUModuleOp m = getOperation();
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MLIRContext *ctx = m.getContext();
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// Request C wrapper emission.
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for (auto func : m.getOps<func::FuncOp>()) {
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func->setAttr(LLVM::LLVMDialect::getEmitCWrapperAttrName(),
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UnitAttr::get(ctx));
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}
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FailureOr<amdgpu::Chipset> maybeChipset = amdgpu::Chipset::parse(chipset);
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if (failed(maybeChipset)) {
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emitError(UnknownLoc::get(ctx), "Invalid chipset name: " + chipset);
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return signalPassFailure();
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}
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/// Customize the bitwidth used for the device side index computations.
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LowerToLLVMOptions options(
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ctx, DataLayout(cast<DataLayoutOpInterface>(m.getOperation())));
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if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout)
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options.overrideIndexBitwidth(indexBitwidth);
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if (useBarePtrCallConv) {
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options.useBarePtrCallConv = true;
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WalkResult canUseBarePointers =
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m.walk([](gpu::GPUFuncOp func) -> WalkResult {
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if (canBeCalledWithBarePointers(func))
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return WalkResult::advance();
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return WalkResult::interrupt();
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});
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if (canUseBarePointers.wasInterrupted()) {
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emitError(UnknownLoc::get(ctx),
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"bare pointer calling convention requires all memrefs to "
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"have static shape and use the identity map");
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return signalPassFailure();
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}
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}
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// Apply in-dialect lowering. In-dialect lowering will replace
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// ops which need to be lowered further, which is not supported by a
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// single conversion pass.
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{
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RewritePatternSet patterns(ctx);
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populateGpuRewritePatterns(patterns);
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arith::populateExpandBFloat16Patterns(patterns);
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(void)applyPatternsAndFoldGreedily(m, std::move(patterns));
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}
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LLVMTypeConverter converter(ctx, options);
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populateGpuMemorySpaceAttributeConversions(
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converter, [](gpu::AddressSpace space) {
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switch (space) {
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case gpu::AddressSpace::Global:
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return 1;
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case gpu::AddressSpace::Workgroup:
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return 3;
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case gpu::AddressSpace::Private:
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return 5;
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}
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llvm_unreachable("unknown address space enum value");
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return 0;
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});
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RewritePatternSet llvmPatterns(ctx);
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mlir::arith::populateArithToLLVMConversionPatterns(converter, llvmPatterns);
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populateAMDGPUToROCDLConversionPatterns(converter, llvmPatterns,
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*maybeChipset);
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populateVectorToLLVMConversionPatterns(converter, llvmPatterns);
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cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns);
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populateFuncToLLVMConversionPatterns(converter, llvmPatterns);
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populateFinalizeMemRefToLLVMConversionPatterns(converter, llvmPatterns);
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populateGpuToROCDLConversionPatterns(converter, llvmPatterns, runtime);
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LLVMConversionTarget target(getContext());
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configureGpuToROCDLConversionLegality(target);
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if (failed(applyPartialConversion(m, target, std::move(llvmPatterns))))
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signalPassFailure();
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// Manually rewrite known block size attributes so the LLVMIR translation
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// infrastructure can pick them up.
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m.walk([ctx](LLVM::LLVMFuncOp op) {
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if (auto blockSizes = dyn_cast_or_null<DenseI32ArrayAttr>(
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op->removeAttr(gpu::GPUFuncOp::getKnownBlockSizeAttrName()))) {
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op->setAttr(ROCDL::ROCDLDialect::getReqdWorkGroupSizeAttrName(),
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blockSizes);
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// Also set up the rocdl.flat_work_group_size attribute to prevent
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// conflicting metadata.
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uint32_t flatSize = 1;
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for (uint32_t size : blockSizes.asArrayRef()) {
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flatSize *= size;
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}
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StringAttr flatSizeAttr =
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StringAttr::get(ctx, Twine(flatSize) + "," + Twine(flatSize));
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op->setAttr(ROCDL::ROCDLDialect::getFlatWorkGroupSizeAttrName(),
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flatSizeAttr);
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}
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});
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}
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};
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} // namespace
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void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) {
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target.addIllegalOp<func::FuncOp>();
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target.addLegalDialect<::mlir::LLVM::LLVMDialect>();
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target.addLegalDialect<ROCDL::ROCDLDialect>();
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target.addIllegalDialect<gpu::GPUDialect>();
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|
target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp,
|
||
|
|
LLVM::FCeilOp, LLVM::FFloorOp, LLVM::FRemOp, LLVM::LogOp,
|
||
|
|
LLVM::Log10Op, LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp,
|
||
|
|
LLVM::SqrtOp>();
|
||
|
|
|
||
|
|
// TODO: Remove once we support replacing non-root ops.
|
||
|
|
target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
|
||
|
|
}
|
||
|
|
|
||
|
|
template <typename OpTy>
|
||
|
|
static void populateOpPatterns(LLVMTypeConverter &converter,
|
||
|
|
RewritePatternSet &patterns, StringRef f32Func,
|
||
|
|
StringRef f64Func) {
|
||
|
|
patterns.add<ScalarizeVectorOpLowering<OpTy>>(converter);
|
||
|
|
patterns.add<OpToFuncCallLowering<OpTy>>(converter, f32Func, f64Func);
|
||
|
|
}
|
||
|
|
|
||
|
|
void mlir::populateGpuToROCDLConversionPatterns(
|
||
|
|
LLVMTypeConverter &converter, RewritePatternSet &patterns,
|
||
|
|
mlir::gpu::amd::Runtime runtime) {
|
||
|
|
using mlir::gpu::amd::Runtime;
|
||
|
|
|
||
|
|
populateWithGenerated(patterns);
|
||
|
|
patterns
|
||
|
|
.add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp,
|
||
|
|
ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>>(
|
||
|
|
converter, gpu::GPUFuncOp::getKnownBlockSizeAttrName());
|
||
|
|
patterns.add<GPUIndexIntrinsicOpLowering<
|
||
|
|
gpu::BlockIdOp, ROCDL::BlockIdXOp, ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>>(
|
||
|
|
converter, gpu::GPUFuncOp::getKnownGridSizeAttrName());
|
||
|
|
patterns
|
||
|
|
.add<GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp,
|
||
|
|
ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>,
|
||
|
|
GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp,
|
||
|
|
ROCDL::GridDimYOp, ROCDL::GridDimZOp>,
|
||
|
|
GPUReturnOpLowering>(converter);
|
||
|
|
patterns.add<GPUFuncOpLowering>(
|
||
|
|
converter,
|
||
|
|
/*allocaAddrSpace=*/ROCDL::ROCDLDialect::kPrivateMemoryAddressSpace,
|
||
|
|
/*workgroupAddrSpace=*/ROCDL::ROCDLDialect::kSharedMemoryAddressSpace,
|
||
|
|
StringAttr::get(&converter.getContext(),
|
||
|
|
ROCDL::ROCDLDialect::getKernelFuncAttrName()));
|
||
|
|
if (Runtime::HIP == runtime) {
|
||
|
|
patterns.add<GPUPrintfOpToHIPLowering>(converter);
|
||
|
|
} else if (Runtime::OpenCL == runtime) {
|
||
|
|
// Use address space = 4 to match the OpenCL definition of printf()
|
||
|
|
patterns.add<GPUPrintfOpToLLVMCallLowering>(converter, /*addressSpace=*/4);
|
||
|
|
}
|
||
|
|
// TODO: Add alignment for workgroup memory
|
||
|
|
patterns.add<GPUDynamicSharedMemoryOpLowering>(converter);
|
||
|
|
|
||
|
|
patterns.add<GPUShuffleOpLowering, GPULaneIdOpToROCDL>(converter);
|
||
|
|
|
||
|
|
populateOpPatterns<math::AbsFOp>(converter, patterns, "__ocml_fabs_f32",
|
||
|
|
"__ocml_fabs_f64");
|
||
|
|
populateOpPatterns<math::AtanOp>(converter, patterns, "__ocml_atan_f32",
|
||
|
|
"__ocml_atan_f64");
|
||
|
|
populateOpPatterns<math::Atan2Op>(converter, patterns, "__ocml_atan2_f32",
|
||
|
|
"__ocml_atan2_f64");
|
||
|
|
populateOpPatterns<math::CbrtOp>(converter, patterns, "__ocml_cbrt_f32",
|
||
|
|
"__ocml_cbrt_f64");
|
||
|
|
populateOpPatterns<math::CeilOp>(converter, patterns, "__ocml_ceil_f32",
|
||
|
|
"__ocml_ceil_f64");
|
||
|
|
populateOpPatterns<math::CosOp>(converter, patterns, "__ocml_cos_f32",
|
||
|
|
"__ocml_cos_f64");
|
||
|
|
populateOpPatterns<math::ExpOp>(converter, patterns, "__ocml_exp_f32",
|
||
|
|
"__ocml_exp_f64");
|
||
|
|
populateOpPatterns<math::Exp2Op>(converter, patterns, "__ocml_exp2_f32",
|
||
|
|
"__ocml_exp2_f64");
|
||
|
|
populateOpPatterns<math::ExpM1Op>(converter, patterns, "__ocml_expm1_f32",
|
||
|
|
"__ocml_expm1_f64");
|
||
|
|
populateOpPatterns<math::FloorOp>(converter, patterns, "__ocml_floor_f32",
|
||
|
|
"__ocml_floor_f64");
|
||
|
|
populateOpPatterns<arith::RemFOp>(converter, patterns, "__ocml_fmod_f32",
|
||
|
|
"__ocml_fmod_f64");
|
||
|
|
populateOpPatterns<math::LogOp>(converter, patterns, "__ocml_log_f32",
|
||
|
|
"__ocml_log_f64");
|
||
|
|
populateOpPatterns<math::Log10Op>(converter, patterns, "__ocml_log10_f32",
|
||
|
|
"__ocml_log10_f64");
|
||
|
|
populateOpPatterns<math::Log1pOp>(converter, patterns, "__ocml_log1p_f32",
|
||
|
|
"__ocml_log1p_f64");
|
||
|
|
populateOpPatterns<math::Log2Op>(converter, patterns, "__ocml_log2_f32",
|
||
|
|
"__ocml_log2_f64");
|
||
|
|
populateOpPatterns<math::PowFOp>(converter, patterns, "__ocml_pow_f32",
|
||
|
|
"__ocml_pow_f64");
|
||
|
|
populateOpPatterns<math::RsqrtOp>(converter, patterns, "__ocml_rsqrt_f32",
|
||
|
|
"__ocml_rsqrt_f64");
|
||
|
|
populateOpPatterns<math::SinOp>(converter, patterns, "__ocml_sin_f32",
|
||
|
|
"__ocml_sin_f64");
|
||
|
|
populateOpPatterns<math::SqrtOp>(converter, patterns, "__ocml_sqrt_f32",
|
||
|
|
"__ocml_sqrt_f64");
|
||
|
|
populateOpPatterns<math::TanhOp>(converter, patterns, "__ocml_tanh_f32",
|
||
|
|
"__ocml_tanh_f64");
|
||
|
|
populateOpPatterns<math::TanOp>(converter, patterns, "__ocml_tan_f32",
|
||
|
|
"__ocml_tan_f64");
|
||
|
|
populateOpPatterns<math::ErfOp>(converter, patterns, "__ocml_erf_f32",
|
||
|
|
"__ocml_erf_f64");
|
||
|
|
}
|
||
|
|
|
||
|
|
std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
|
||
|
|
mlir::createLowerGpuOpsToROCDLOpsPass(const std::string &chipset,
|
||
|
|
unsigned indexBitwidth,
|
||
|
|
bool useBarePtrCallConv,
|
||
|
|
gpu::amd::Runtime runtime) {
|
||
|
|
return std::make_unique<LowerGpuOpsToROCDLOpsPass>(
|
||
|
|
chipset, indexBitwidth, useBarePtrCallConv, runtime);
|
||
|
|
}
|