# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 # RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32 # RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64 --- name: float_imm legalized: true regBankSelected: true body: | bb.1: ; RV32-LABEL: name: float_imm ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 263313 ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -37 ; RV32-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDI]] ; RV32-NEXT: $f10_f = COPY [[FMV_W_X]] ; RV32-NEXT: PseudoRET implicit $f10_f ; ; RV64-LABEL: name: float_imm ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 263313 ; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -37 ; RV64-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDIW]] ; RV64-NEXT: $f10_f = COPY [[FMV_W_X]] ; RV64-NEXT: PseudoRET implicit $f10_f %0:fprb(s32) = G_FCONSTANT float 0x400921FB60000000 $f10_f = COPY %0(s32) PseudoRET implicit $f10_f ... --- name: float_imm_op legalized: true regBankSelected: true body: | bb.1: liveins: $f10_f ; CHECK-LABEL: name: float_imm_op ; CHECK: liveins: $f10_f ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 260096 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]] ; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[FMV_W_X]], 7 ; CHECK-NEXT: $f10_f = COPY [[FADD_S]] ; CHECK-NEXT: PseudoRET implicit $f10_f %0:fprb(s32) = COPY $f10_f %1:fprb(s32) = G_FCONSTANT float 1.000000e+00 %2:fprb(s32) = G_FADD %0, %1 $f10_f = COPY %2(s32) PseudoRET implicit $f10_f ... --- name: float_positive_zero legalized: true regBankSelected: true body: | bb.1: liveins: $x10 ; CHECK-LABEL: name: float_positive_zero ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]] ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]] ; CHECK-NEXT: PseudoRET implicit $f10_f %1:fprb(s32) = G_FCONSTANT float 0.000000e+00 $f10_f = COPY %1(s32) PseudoRET implicit $f10_f ... --- name: float_negative_zero legalized: true regBankSelected: true body: | bb.1: liveins: $x10 ; CHECK-LABEL: name: float_negative_zero ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 ; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]] ; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]] ; CHECK-NEXT: PseudoRET implicit $f10_f %1:fprb(s32) = G_FCONSTANT float -0.000000e+00 $f10_f = COPY %1(s32) PseudoRET implicit $f10_f ... --- name: double_imm legalized: true regBankSelected: true body: | bb.1: ; RV32-LABEL: name: double_imm ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 262290 ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 507 ; RV32-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI 345155 ; RV32-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[LUI1]], -744 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[ADDI1]], [[ADDI]] ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]] ; RV32-NEXT: PseudoRET implicit $f10_d ; ; RV64-LABEL: name: double_imm ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 512 ; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 1169 ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDIW]], 15 ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], -299 ; RV64-NEXT: [[SLLI1:%[0-9]+]]:gpr = SLLI [[ADDI]], 14 ; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI1]], 1091 ; RV64-NEXT: [[SLLI2:%[0-9]+]]:gpr = SLLI [[ADDI1]], 12 ; RV64-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[SLLI2]], -744 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[ADDI2]] ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]] ; RV64-NEXT: PseudoRET implicit $f10_d %0:fprb(s64) = G_FCONSTANT double 0x400921FB54442D18 $f10_d = COPY %0(s64) PseudoRET implicit $f10_d ... --- name: double_imm_op legalized: true regBankSelected: true body: | bb.1: liveins: $f10_d ; RV32-LABEL: name: double_imm_op ; RV32: liveins: $f10_d ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d ; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 261888 ; RV32-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[LUI]] ; RV32-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[BuildPairF64Pseudo]], 7 ; RV32-NEXT: $f10_d = COPY [[FADD_D]] ; RV32-NEXT: PseudoRET implicit $f10_d ; ; RV64-LABEL: name: double_imm_op ; RV64: liveins: $f10_d ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1023 ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 52 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]] ; RV64-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[FMV_D_X]], 7 ; RV64-NEXT: $f10_d = COPY [[FADD_D]] ; RV64-NEXT: PseudoRET implicit $f10_d %0:fprb(s64) = COPY $f10_d %1:fprb(s64) = G_FCONSTANT double 1.000000e+00 %2:fprb(s64) = G_FADD %0, %1 $f10_d = COPY %2(s64) PseudoRET implicit $f10_d ... --- name: double_positive_zero legalized: true regBankSelected: true body: | bb.1: liveins: $x10 ; RV32-LABEL: name: double_positive_zero ; RV32: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; RV32-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[COPY]] ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]] ; RV32-NEXT: PseudoRET implicit $f10_d ; ; RV64-LABEL: name: double_positive_zero ; RV64: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[COPY]] ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]] ; RV64-NEXT: PseudoRET implicit $f10_d %1:fprb(s64) = G_FCONSTANT double 0.000000e+00 $f10_d = COPY %1(s64) PseudoRET implicit $f10_d ... --- name: double_negative_zero legalized: true regBankSelected: true body: | bb.1: liveins: $x10 ; RV32-LABEL: name: double_negative_zero ; RV32: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288 ; RV32-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[LUI]] ; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]] ; RV32-NEXT: PseudoRET implicit $f10_d ; ; RV64-LABEL: name: double_negative_zero ; RV64: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1 ; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63 ; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]] ; RV64-NEXT: $f10_d = COPY [[FMV_D_X]] ; RV64-NEXT: PseudoRET implicit $f10_d %1:fprb(s64) = G_FCONSTANT double -0.000000e+00 $f10_d = COPY %1(s64) PseudoRET implicit $f10_d ...