; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm < %s | FileCheck %s ; ; LD1ROB ; define @ld1rob_i8( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1rob_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x1] ; CHECK-NEXT: ret %base = getelementptr i8, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv16i8( %pg, ptr %base) ret %load } ; ; LD1ROH ; define @ld1roh_i16( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1roh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x1, lsl #1] ; CHECK-NEXT: ret %base = getelementptr i16, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv8i16( %pg, ptr %base) ret %load } define @ld1roh_f16( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1roh_f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x1, lsl #1] ; CHECK-NEXT: ret %base = getelementptr half, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv8f16( %pg, ptr %base) ret %load } define @ld1roh_bf16( %pg, ptr %a, i64 %index) #0 { ; CHECK-LABEL: ld1roh_bf16: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x1, lsl #1] ; CHECK-NEXT: ret %base = getelementptr bfloat, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv8bf16( %pg, ptr %base) ret %load } ; ; LD1ROW ; define @ld1row_i32( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1row_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x1, lsl #2] ; CHECK-NEXT: ret %base = getelementptr i32, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv4i32( %pg, ptr %base) ret %load } define @ld1row_f32( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1row_f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x1, lsl #2] ; CHECK-NEXT: ret %base = getelementptr float, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv4f32( %pg, ptr %base) ret %load } ; ; LD1ROD ; define @ld1rod_i64( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1rod_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, x1, lsl #3] ; CHECK-NEXT: ret %base = getelementptr i64, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv2i64( %pg, ptr %base) ret %load } define @ld1rod_f64( %pg, ptr %a, i64 %index) { ; CHECK-LABEL: ld1rod_f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, x1, lsl #3] ; CHECK-NEXT: ret %base = getelementptr double, ptr %a, i64 %index %load = call @llvm.aarch64.sve.ld1ro.nxv2f64( %pg, ptr %base) ret %load } declare @llvm.aarch64.sve.ld1ro.nxv16i8(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv8i16(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv8f16(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv8bf16(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv4i32(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv4f32(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv2i64(, ptr) declare @llvm.aarch64.sve.ld1ro.nxv2f64(, ptr) ; +bf16 is required for the bfloat version. attributes #0 = { "target-features"="+sve,+f64mm,+bf16" }