# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s

---
name:            brcond
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; RV32I-LABEL: name: brcond
  ; RV32I: bb.0:
  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x12
  ; RV32I-NEXT:   [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BEQ [[LW]], [[COPY]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.1
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.1:
  ; RV32I-NEXT:   [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BNE [[LW1]], [[COPY]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.2
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.2:
  ; RV32I-NEXT:   [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BLT [[LW2]], [[COPY]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.3
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.3:
  ; RV32I-NEXT:   [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BGE [[LW3]], [[COPY]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.4
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.4:
  ; RV32I-NEXT:   [[LW4:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BLTU [[LW4]], [[COPY]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.5
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.5:
  ; RV32I-NEXT:   [[LW5:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BGEU [[LW5]], [[COPY]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.6
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.6:
  ; RV32I-NEXT:   [[LW6:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BLT [[COPY]], [[LW6]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.7
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.7:
  ; RV32I-NEXT:   [[LW7:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BGE [[COPY]], [[LW7]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.8
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.8:
  ; RV32I-NEXT:   [[LW8:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BLTU [[COPY]], [[LW8]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.9
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.9:
  ; RV32I-NEXT:   [[LW9:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BGEU [[COPY]], [[LW9]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.10
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.10:
  ; RV32I-NEXT:   [[LW10:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
  ; RV32I-NEXT:   BNE [[ANDI]], $x0, %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.11
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.11:
  ; RV32I-NEXT:   successors: %bb.14(0x50000000), %bb.12(0x30000000)
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT:   [[LW11:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BGE [[LW11]], $x0, %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.12
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.12:
  ; RV32I-NEXT:   successors: %bb.14(0x30000000), %bb.13(0x50000000)
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT:   [[LW12:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT:   BGE $x0, [[LW12]], %bb.14
  ; RV32I-NEXT:   PseudoBR %bb.13
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.13:
  ; RV32I-NEXT:   [[LW13:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.14:
  ; RV32I-NEXT:   PseudoRET
  bb.1:
    liveins: $x10, $x11, $x12

    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = COPY $x11
    %3:gprb(s32) = COPY $x12
    %26:gprb(s32) = G_CONSTANT i32 -1
    %29:gprb(s32) = G_CONSTANT i32 1
    %4:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %56:gprb(s32) = G_ICMP intpred(eq), %4(s32), %0
    G_BRCOND %56(s32), %bb.15
    G_BR %bb.2

  bb.2:
    %6:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %54:gprb(s32) = G_ICMP intpred(ne), %6(s32), %0
    G_BRCOND %54(s32), %bb.15
    G_BR %bb.3

  bb.3:
    %8:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %52:gprb(s32) = G_ICMP intpred(slt), %8(s32), %0
    G_BRCOND %52(s32), %bb.15
    G_BR %bb.4

  bb.4:
    %10:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %50:gprb(s32) = G_ICMP intpred(sge), %10(s32), %0
    G_BRCOND %50(s32), %bb.15
    G_BR %bb.5

  bb.5:
    %12:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %48:gprb(s32) = G_ICMP intpred(ult), %12(s32), %0
    G_BRCOND %48(s32), %bb.15
    G_BR %bb.6

  bb.6:
    %14:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %46:gprb(s32) = G_ICMP intpred(uge), %14(s32), %0
    G_BRCOND %46(s32), %bb.15
    G_BR %bb.7

  bb.7:
    %16:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %44:gprb(s32) = G_ICMP intpred(sgt), %16(s32), %0
    G_BRCOND %44(s32), %bb.15
    G_BR %bb.8

  bb.8:
    %18:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %42:gprb(s32) = G_ICMP intpred(sle), %18(s32), %0
    G_BRCOND %42(s32), %bb.15
    G_BR %bb.9

  bb.9:
    %20:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %40:gprb(s32) = G_ICMP intpred(ugt), %20(s32), %0
    G_BRCOND %40(s32), %bb.15
    G_BR %bb.10

  bb.10:
    %22:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %38:gprb(s32) = G_ICMP intpred(ule), %22(s32), %0
    G_BRCOND %38(s32), %bb.15
    G_BR %bb.11

  bb.11:
    %24:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %57:gprb(s32) = G_CONSTANT i32 1
    %36:gprb(s32) = G_AND %3, %57
    G_BRCOND %36(s32), %bb.15
    G_BR %bb.12

  bb.12:
    successors: %bb.15(0x50000000), %bb.13(0x30000000)

    %25:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %35:gprb(s32) = G_ICMP intpred(sgt), %25(s32), %26
    G_BRCOND %35(s32), %bb.15
    G_BR %bb.13

  bb.13:
    successors: %bb.15(0x30000000), %bb.14(0x50000000)

    %28:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
    %33:gprb(s32) = G_ICMP intpred(slt), %28(s32), %29
    G_BRCOND %33(s32), %bb.15
    G_BR %bb.14

  bb.14:
    %31:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))

  bb.15:
    PseudoRET

...