# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -timeline -iterations=1 < %s | FileCheck %s # PR51495: WriteIMulH reports an incorrect latency for the RM variants of MULX. # LLVM-MCA-BEGIN mulxl (%rdi), %eax, %ecx add %eax, %eax # LLVM-MCA-END # LLVM-MCA-BEGIN mulxq (%rdi), %rax, %rcx add %rax, %rax # LLVM-MCA-END # CHECK: [0] Code Region # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total uOps: 6 # CHECK: Dispatch Width: 6 # CHECK-NEXT: uOps Per Cycle: 0.50 # CHECK-NEXT: IPC: 0.17 # CHECK-NEXT: Block RThroughput: 1.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 5 9 1.00 * mulxl (%rdi), %eax, %ecx # CHECK-NEXT: 1 1 0.25 addl %eax, %eax # CHECK: Resources: # CHECK-NEXT: [0] - SKLDivider # CHECK-NEXT: [1] - SKLFPDivider # CHECK-NEXT: [2] - SKLPort0 # CHECK-NEXT: [3] - SKLPort1 # CHECK-NEXT: [4] - SKLPort2 # CHECK-NEXT: [5] - SKLPort3 # CHECK-NEXT: [6] - SKLPort4 # CHECK-NEXT: [7] - SKLPort5 # CHECK-NEXT: [8] - SKLPort6 # CHECK-NEXT: [9] - SKLPort7 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] # CHECK-NEXT: - - 1.00 1.00 - 1.00 - 1.00 1.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: - - - 1.00 - 1.00 - 1.00 1.00 - mulxl (%rdi), %eax, %ecx # CHECK-NEXT: - - 1.00 - - - - - - - addl %eax, %eax # CHECK: Timeline view: # CHECK-NEXT: 01 # CHECK-NEXT: Index 0123456789 # CHECK: [0,0] DeeeeeeeeeER mulxl (%rdi), %eax, %ecx # CHECK-NEXT: [0,1] D========eER addl %eax, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 mulxl (%rdi), %eax, %ecx # CHECK-NEXT: 1. 1 9.0 0.0 0.0 addl %eax, %eax # CHECK-NEXT: 1 5.0 0.5 0.0 # CHECK: [1] Code Region # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total uOps: 5 # CHECK: Dispatch Width: 6 # CHECK-NEXT: uOps Per Cycle: 0.42 # CHECK-NEXT: IPC: 0.17 # CHECK-NEXT: Block RThroughput: 1.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 4 9 1.00 * mulxq (%rdi), %rax, %rcx # CHECK-NEXT: 1 1 0.25 addq %rax, %rax # CHECK: Resources: # CHECK-NEXT: [0] - SKLDivider # CHECK-NEXT: [1] - SKLFPDivider # CHECK-NEXT: [2] - SKLPort0 # CHECK-NEXT: [3] - SKLPort1 # CHECK-NEXT: [4] - SKLPort2 # CHECK-NEXT: [5] - SKLPort3 # CHECK-NEXT: [6] - SKLPort4 # CHECK-NEXT: [7] - SKLPort5 # CHECK-NEXT: [8] - SKLPort6 # CHECK-NEXT: [9] - SKLPort7 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] # CHECK-NEXT: - - - 1.00 - 1.00 - 1.00 1.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: - - - 1.00 - 1.00 - 1.00 - - mulxq (%rdi), %rax, %rcx # CHECK-NEXT: - - - - - - - - 1.00 - addq %rax, %rax # CHECK: Timeline view: # CHECK-NEXT: 01 # CHECK-NEXT: Index 0123456789 # CHECK: [0,0] DeeeeeeeeeER mulxq (%rdi), %rax, %rcx # CHECK-NEXT: [0,1] D========eER addq %rax, %rax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 mulxq (%rdi), %rax, %rcx # CHECK-NEXT: 1. 1 9.0 0.0 0.0 addq %rax, %rax # CHECK-NEXT: 1 5.0 0.5 0.0