; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; RUN: opt -loop-reduce -S < %s | FileCheck %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2" target triple = "x86_64-unknown-linux-gnu" define void @test() { ; CHECK-LABEL: define void @test() { ; CHECK-NEXT: bb: ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: bb3: ; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB7:%.*]] ], [ 0, [[BB:%.*]] ] ; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB7]] ], [ 16, [[BB]] ] ; CHECK-NEXT: br label [[BB4:%.*]] ; CHECK: bb4: ; CHECK-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[BB6:%.*]] ], [ [[LSR_IV1]], [[BB3]] ] ; CHECK-NEXT: br i1 true, label [[BB7]], label [[BB6]] ; CHECK: bb6: ; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i32 [[LSR_IV3]], 268435456 ; CHECK-NEXT: br label [[BB4]] ; CHECK: bb7: ; CHECK-NEXT: [[MUL9:%.*]] = mul i32 [[LSR_IV3]], [[LSR_IV3]] ; CHECK-NEXT: [[MUL10:%.*]] = mul i32 [[MUL9]], [[LSR_IV3]] ; CHECK-NEXT: call void @foo(i32 [[MUL10]]) ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[MUL10]] to i64 ; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 32 ; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], [[LSR_IV]] ; CHECK-NEXT: br label [[BB3]] ; bb: br label %bb3 bb3: ; preds = %bb7, %bb %phi = phi i64 [ 0, %bb ], [ %add11, %bb7 ] br label %bb4 bb4: ; preds = %bb6, %bb3 %phi5 = phi i32 [ 0, %bb3 ], [ %add, %bb6 ] br i1 true, label %bb7, label %bb6 bb6: ; preds = %bb4 %add = add i32 %phi5, 8 br label %bb4 bb7: ; preds = %bb4 %shl = shl i32 %phi5, 25 %mul = mul i64 %phi, %phi %trunc = trunc i64 %mul to i32 %add8 = add i32 %shl, %trunc %mul9 = mul i32 %add8, %add8 %mul10 = mul i32 %mul9, %add8 call void @foo(i32 %mul10) %sext = sext i32 %mul10 to i64 %add11 = add i64 %phi, 4 br label %bb3 } declare void @foo(i32)