# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
---
name:            test_icmp
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_icmp
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
    ; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
    ; CHECK-NEXT: $w0 = COPY [[ICMP1]](s32)
    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
    ; CHECK-NEXT: $w0 = COPY [[ICMP2]](s32)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x0
    %2:_(s8) = G_TRUNC %0(s64)
    %3:_(s8) = G_TRUNC %1(s64)
    %4:_(s1) = G_ICMP intpred(sge), %0(s64), %1
    %11:_(s32) = G_ANYEXT %4(s1)
    $w0 = COPY %11(s32)
    %8:_(s1) = G_ICMP intpred(ult), %2(s8), %3
    %12:_(s32) = G_ANYEXT %8(s1)
    $w0 = COPY %12(s32)
    %9:_(p0) = G_INTTOPTR %0(s64)
    %10:_(s1) = G_ICMP intpred(eq), %9(p0), %9
    %14:_(s32) = G_ANYEXT %10(s1)
    $w0 = COPY %14(s32)

...
---
name:            test_s128
alignment:       4
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s128
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
  ; CHECK-NEXT:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
  ; CHECK-NEXT:   [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
  ; CHECK-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
  ; CHECK-NEXT:   G_BRCOND [[SELECT]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %0:_(s128) = G_IMPLICIT_DEF
    %1:_(s128) = G_CONSTANT i128 79228162514264337593543950336
    %3:_(s1) = G_CONSTANT i1 true
    %2:_(s1) = G_ICMP intpred(ult), %0(s128), %1
    G_BRCOND %2(s1), %bb.2
    G_BR %bb.3

  bb.2:
    successors:


  bb.3:
    RET_ReallyLR

...
---
name:            test_s128_eq
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s128_eq
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
  ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C]]
  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %lhs:_(s128) = G_IMPLICIT_DEF
    %rhs:_(s128) = G_IMPLICIT_DEF
    %cmp:_(s1) = G_ICMP intpred(eq), %lhs(s128), %rhs
    G_BRCOND %cmp(s1), %bb.2
    G_BR %bb.3
  bb.2:
    successors:
  bb.3:
    RET_ReallyLR

...
---
name:            test_s88_eq
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s88_eq
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
  ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %lhs:_(s88) = G_IMPLICIT_DEF
    %rhs:_(s88) = G_IMPLICIT_DEF
    %cmp:_(s1) = G_ICMP intpred(eq), %lhs(s88), %rhs
    G_BRCOND %cmp(s1), %bb.2
    G_BR %bb.3
  bb.2:
    successors:
  bb.3:
    RET_ReallyLR

...
---
name:            test_s88_ne
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s88_ne
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
  ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C2]]
  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %lhs:_(s88) = G_IMPLICIT_DEF
    %rhs:_(s88) = G_IMPLICIT_DEF
    %cmp:_(s1) = G_ICMP intpred(ne), %lhs(s88), %rhs
    G_BRCOND %cmp(s1), %bb.2
    G_BR %bb.3
  bb.2:
    successors:
  bb.3:
    RET_ReallyLR

...
---
name:            test_s96_eq
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s96_eq
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND2]]
  ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %lhs:_(s96) = G_IMPLICIT_DEF
    %rhs:_(s96) = G_IMPLICIT_DEF
    %cmp:_(s1) = G_ICMP intpred(eq), %lhs(s96), %rhs
    G_BRCOND %cmp(s1), %bb.2
    G_BR %bb.3
  bb.2:
    successors:
  bb.3:
    RET_ReallyLR
...
---
name:            test_s318_eq
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s318_eq
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND5:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[AND6:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[AND7:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[AND8:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND9:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND10:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND11:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND12:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND13:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[AND14:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[AND15:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND8]]
  ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND9]]
  ; CHECK-NEXT:   [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND10]]
  ; CHECK-NEXT:   [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND11]]
  ; CHECK-NEXT:   [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[AND4]], [[AND12]]
  ; CHECK-NEXT:   [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[AND5]], [[AND13]]
  ; CHECK-NEXT:   [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[AND6]], [[AND14]]
  ; CHECK-NEXT:   [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[AND7]], [[AND15]]
  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
  ; CHECK-NEXT:   [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
  ; CHECK-NEXT:   [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
  ; CHECK-NEXT:   [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[XOR4]]
  ; CHECK-NEXT:   [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[XOR5]]
  ; CHECK-NEXT:   [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[XOR6]]
  ; CHECK-NEXT:   [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[XOR7]]
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR6]](s64), [[C2]]
  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %lhs:_(s318) = G_IMPLICIT_DEF
    %rhs:_(s318) = G_IMPLICIT_DEF
    %cmp:_(s1) = G_ICMP intpred(eq), %lhs(s318), %rhs
    G_BRCOND %cmp(s1), %bb.2
    G_BR %bb.3
  bb.2:
    successors:
  bb.3:
    RET_ReallyLR
...
---
name:            test_s158_eq
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_s158_eq
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1073741823
  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND5:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
  ; CHECK-NEXT:   [[AND6:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C1]]
  ; CHECK-NEXT:   [[AND7:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C2]]
  ; CHECK-NEXT:   [[XOR:%[0-9]+]]:_(s64) = G_XOR [[AND]], [[AND4]]
  ; CHECK-NEXT:   [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND5]]
  ; CHECK-NEXT:   [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[AND2]], [[AND6]]
  ; CHECK-NEXT:   [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[AND3]], [[AND7]]
  ; CHECK-NEXT:   [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
  ; CHECK-NEXT:   [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
  ; CHECK-NEXT:   [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR2]](s64), [[C2]]
  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.1
  ; CHECK-NEXT:   G_BR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors:
  ; CHECK: bb.2:
  ; CHECK-NEXT:   RET_ReallyLR
  bb.1:
    %lhs:_(s158) = G_IMPLICIT_DEF
    %rhs:_(s158) = G_IMPLICIT_DEF
    %cmp:_(s1) = G_ICMP intpred(eq), %lhs(s158), %rhs
    G_BRCOND %cmp(s1), %bb.2
    G_BR %bb.3
  bb.2:
    successors:
  bb.3:
    RET_ReallyLR
...
---
name:            test_3xs32_eq_pr_78181
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_3xs32_eq_pr_78181
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ICMP]](<4 x s32>), [[C]](s64)
    ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s32) = G_IMPLICIT_DEF
    %rhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
    %lhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32)
    %cmp:_(<3 x s32>) = G_ICMP intpred(eq), %lhs(<3 x s32>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s32)
    $w0 = COPY %2(s32)
    RET_ReallyLR
...
---
name:            test_3xs16_eq_pr_78181
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_3xs16_eq_pr_78181
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s16>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[ICMP]](<4 x s16>)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR2]](<4 x s32>), [[C]](s64)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: %zext:_(s32) = G_AND [[EVEC]], [[C1]]
    ; CHECK-NEXT: $w0 = COPY %zext(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s16) = G_IMPLICIT_DEF
    %rhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16)
    %lhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16)
    %cmp:_(<3 x s16>) = G_ICMP intpred(eq), %lhs(<3 x s16>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s16>), %1(s32)
    %zext:_(s32) = G_ZEXT %2(s16)
    $w0 = COPY %zext(s32)
    RET_ReallyLR
...
---
name:            test_3xs8_eq_pr_78181
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_3xs8_eq_pr_78181
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<8 x s8>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[ICMP]](<8 x s8>)
    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UV]](<4 x s8>)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[DEF]](s32)
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR2]](<4 x s32>), [[C]](s64)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: %zext:_(s32) = G_AND [[EVEC]], [[C1]]
    ; CHECK-NEXT: $w0 = COPY %zext(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s8) = G_IMPLICIT_DEF
    %rhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8)
    %lhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8)
    %cmp:_(<3 x s8>) = G_ICMP intpred(eq), %lhs(<3 x s8>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s8>), %1(s32)
    %zext:_(s32) = G_ZEXT %2(s8)
    $w0 = COPY %zext(s32)
    RET_ReallyLR
...
---
name:            test_3xs64_eq_clamp
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_3xs64_eq_clamp
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s64) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<2 x s64>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[ICMP]](<2 x s64>), [[C]](s64)
    ; CHECK-NEXT: $x0 = COPY [[EVEC]](s64)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s64) = G_IMPLICIT_DEF
    %rhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64)
    %lhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64)
    %cmp:_(<3 x s64>) = G_ICMP intpred(eq), %lhs(<3 x s64>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s64) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s64>), %1(s32)
    $x0 = COPY %2(s64)
    RET_ReallyLR
...
---
name:            test_5xs32_eq_clamp
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_5xs32_eq_clamp
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ICMP]](<4 x s32>), [[C]](s64)
    ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s32) = G_IMPLICIT_DEF
    %rhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32)
    %lhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32)
    %cmp:_(<5 x s32>) = G_ICMP intpred(eq), %lhs(<5 x s32>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<5 x s32>), %1(s32)
    $w0 = COPY %2(s32)
    RET_ReallyLR
...
---
name:            test_7xs16_eq_clamp
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_7xs16_eq_clamp
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<8 x s16>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[ICMP]](<8 x s16>), [[C]](s64)
    ; CHECK-NEXT: %zext:_(s32) = G_ZEXT [[EVEC]](s16)
    ; CHECK-NEXT: $w0 = COPY %zext(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s16) = G_IMPLICIT_DEF
    %rhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
    %lhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16)
    %cmp:_(<7 x s16>) = G_ICMP intpred(eq), %lhs(<7 x s16>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<7 x s16>), %1(s32)
    %zext:_(s32) = G_ZEXT %2(s16)
    $w0 = COPY %zext(s32)
    RET_ReallyLR
...
---
name:            test_9xs8_eq_clamp
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0
    ; CHECK-LABEL: name: test_9xs8_eq_clamp
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %const:_(s8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[BUILD_VECTOR]](<16 x s8>), [[BUILD_VECTOR1]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[ICMP]](<16 x s8>), [[C]](s64)
    ; CHECK-NEXT: %zext:_(s32) = G_ZEXT [[EVEC]](s8)
    ; CHECK-NEXT: $w0 = COPY %zext(s32)
    ; CHECK-NEXT: RET_ReallyLR
    %const:_(s8) = G_IMPLICIT_DEF
    %rhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
    %lhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8)
    %cmp:_(<9 x s8>) = G_ICMP intpred(eq), %lhs(<9 x s8>), %rhs
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<9 x s8>), %1(s32)
    %zext:_(s32) = G_ZEXT %2(s8)
    $w0 = COPY %zext(s32)
    RET_ReallyLR