# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-uknown -global-isel-abort=1 -run-pass=instruction-select %s -o - | FileCheck %s
...
---
name:            ssube_s64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: ssube_s64
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr $wzr, [[MOVi32imm]], implicit-def $nzcv
    ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY]], [[COPY1]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
    ; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $w1
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = COPY $x1
    %2:gpr(s32) = G_CONSTANT i32 1
    %3:gpr(s64), %4:gpr(s32) = G_SSUBE %0, %1, %2
    $x0 = COPY %3(s64)
    $w1 = COPY %4(s32)
    RET_ReallyLR implicit $x0, implicit $w1
...
...
---
name:            ssube_s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: ssube_s32
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr $wzr, [[MOVi32imm]], implicit-def $nzcv
    ; CHECK-NEXT: [[SBCSWr:%[0-9]+]]:gpr32 = SBCSWr [[COPY]], [[COPY1]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[SBCSWr]]
    ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = COPY $w1
    %2:gpr(s32) = G_CONSTANT i32 1
    %3:gpr(s32), %4:gpr(s32) = G_SSUBE %0, %1, %2
    $w0 = COPY %3(s32)
    $w1 = COPY %4(s32)
    RET_ReallyLR implicit $w0, implicit $w1
...
...
---
name:            ssube_opt_prev_usubo
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0, $x1, $x2, $x3

    ; CHECK-LABEL: name: ssube_opt_prev_usubo
    ; CHECK: liveins: $x0, $x1, $x2, $x3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
    ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
    ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
    ; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = COPY $x1
    %2:gpr(s64) = COPY $x2
    %3:gpr(s64) = COPY $x3
    %8:gpr(s64), %12:gpr(s32) = G_USUBO %0, %2
    %9:gpr(s64), %13:gpr(s32) = G_SSUBE %1, %3, %12
    $x0 = COPY %8(s64)
    $x1 = COPY %9(s64)
    RET_ReallyLR implicit $x0, implicit $x1
...
...
---
name:            ssube_opt_prev_usube
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0, $x1, $x2, $x3

    ; CHECK-LABEL: name: ssube_opt_prev_usube
    ; CHECK: liveins: $x0, $x1, $x2, $x3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr $wzr, [[MOVi32imm]], implicit-def $nzcv
    ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY]], [[COPY2]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: [[SBCSXr1:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: $x0 = COPY [[SBCSXr]]
    ; CHECK-NEXT: $x1 = COPY [[SBCSXr1]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = COPY $x1
    %2:gpr(s64) = COPY $x2
    %3:gpr(s64) = COPY $x3
    %6:gpr(s32) = G_CONSTANT i32 1
    %8:gpr(s64), %12:gpr(s32) = G_USUBE %0, %2, %6
    %9:gpr(s64), %13:gpr(s32) = G_SSUBE %1, %3, %12
    $x0 = COPY %8(s64)
    $x1 = COPY %9(s64)
    RET_ReallyLR implicit $x0, implicit $x1
...
...
---
name:            ssube_opt_bail_clobber
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0, $x1, $x2, $x4, $x5, $x6

    ; CHECK-LABEL: name: ssube_opt_bail_clobber
    ; CHECK: liveins: $x0, $x1, $x2, $x4, $x5, $x6
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x4
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY $x5
    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr64 = COPY $x6
    ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY3]], implicit-def $nzcv
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
    ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY4]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr $wzr, [[CSINCWr]], implicit-def $nzcv
    ; CHECK-NEXT: [[SBCSXr1:%[0-9]+]]:gpr64 = SBCSXr [[COPY2]], [[COPY5]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
    ; CHECK-NEXT: $x1 = COPY [[SBCSXr]]
    ; CHECK-NEXT: $x2 = COPY [[SBCSXr1]]
    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = COPY $x1
    %2:gpr(s64) = COPY $x2
    %4:gpr(s64) = COPY $x4
    %5:gpr(s64) = COPY $x5
    %6:gpr(s64) = COPY $x6
    %7:gpr(s64), %11:gpr(s32) = G_USUBO %0, %4
    %8:gpr(s64), %12:gpr(s32) = G_USUBE %1, %5, %11
    ; carry-in is not produced by previous instruction
    %9:gpr(s64), %13:gpr(s32) = G_SSUBE %2, %6, %11
    $x0 = COPY %7(s64)
    $x1 = COPY %8(s64)
    $x2 = COPY %9(s64)
    RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
---
name:            ssube_opt_prev_dead
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0, $x1, $x2, $x3
    ; CHECK-LABEL: name: ssube_opt_prev_dead
    ; CHECK: liveins: $x0, $x1, $x2, $x3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
    ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
    ; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = COPY $x1
    %2:gpr(s64) = COPY $x2
    %3:gpr(s64) = COPY $x3
    %4:gpr(s64), %5:gpr(s32) = G_USUBO %0, %2
    %6:gpr(s64), %7:gpr(s32) = G_SSUBE %1, %3, %5
    $w0 = COPY %7(s32)
    RET_ReallyLR implicit $w0
...