; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,CHECK-SD %s
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

; CHECK-GI:       warning: Instruction selection used fallback path for abs_8b
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_16b
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_4h
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_8h
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_2s
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_4s
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_1d
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for abs_1d_honestly
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for fabds
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for fabdd
; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for uabd_i64

define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    sabdl.8h v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
  ret <8 x i16> %tmp4
}

define <4 x i32> @sabdl4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    sabdl.4s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
  ret <4 x i32> %tmp4
}

define <2 x i64> @sabdl2d(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl2d:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    sabdl.2d v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
  ret <2 x i64> %tmp4
}

define <8 x i16> @sabdl2_8h(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: sabdl2_8h:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d0, [x0, #8]
; CHECK-SD-NEXT:    ldr d1, [x1, #8]
; CHECK-SD-NEXT:    sabdl.8h v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabdl2_8h:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q0, [x0]
; CHECK-GI-NEXT:    ldr q1, [x1]
; CHECK-GI-NEXT:    sabdl2.8h v0, v0, v1
; CHECK-GI-NEXT:    ret
  %load1 = load <16 x i8>, ptr %A
  %load2 = load <16 x i8>, ptr %B
  %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
  ret <8 x i16> %tmp4
}

define <4 x i32> @sabdl2_4s(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: sabdl2_4s:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d0, [x0, #8]
; CHECK-SD-NEXT:    ldr d1, [x1, #8]
; CHECK-SD-NEXT:    sabdl.4s v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabdl2_4s:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q0, [x0]
; CHECK-GI-NEXT:    ldr q1, [x1]
; CHECK-GI-NEXT:    sabdl2.4s v0, v0, v1
; CHECK-GI-NEXT:    ret
  %load1 = load <8 x i16>, ptr %A
  %load2 = load <8 x i16>, ptr %B
  %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
  ret <4 x i32> %tmp4
}

define <2 x i64> @sabdl2_2d(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: sabdl2_2d:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d0, [x0, #8]
; CHECK-SD-NEXT:    ldr d1, [x1, #8]
; CHECK-SD-NEXT:    sabdl.2d v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabdl2_2d:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q0, [x0]
; CHECK-GI-NEXT:    ldr q1, [x1]
; CHECK-GI-NEXT:    sabdl2.2d v0, v0, v1
; CHECK-GI-NEXT:    ret
  %load1 = load <4 x i32>, ptr %A
  %load2 = load <4 x i32>, ptr %B
  %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
  ret <2 x i64> %tmp4
}

define <8 x i16> @uabdl8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabdl8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uabdl.8h v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
  ret <8 x i16> %tmp4
}

define <4 x i32> @uabdl4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabdl4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uabdl.4s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
  ret <4 x i32> %tmp4
}

define <2 x i64> @uabdl2d(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabdl2d:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uabdl.2d v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
  ret <2 x i64> %tmp4
}

define <8 x i16> @uabdl2_8h(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: uabdl2_8h:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d0, [x0, #8]
; CHECK-SD-NEXT:    ldr d1, [x1, #8]
; CHECK-SD-NEXT:    uabdl.8h v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabdl2_8h:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q0, [x0]
; CHECK-GI-NEXT:    ldr q1, [x1]
; CHECK-GI-NEXT:    uabdl2.8h v0, v0, v1
; CHECK-GI-NEXT:    ret
  %load1 = load <16 x i8>, ptr %A
  %load2 = load <16 x i8>, ptr %B
  %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>

  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
  ret <8 x i16> %tmp4
}

define <4 x i32> @uabdl2_4s(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: uabdl2_4s:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d0, [x0, #8]
; CHECK-SD-NEXT:    ldr d1, [x1, #8]
; CHECK-SD-NEXT:    uabdl.4s v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabdl2_4s:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q0, [x0]
; CHECK-GI-NEXT:    ldr q1, [x1]
; CHECK-GI-NEXT:    uabdl2.4s v0, v0, v1
; CHECK-GI-NEXT:    ret
  %load1 = load <8 x i16>, ptr %A
  %load2 = load <8 x i16>, ptr %B
  %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
  ret <4 x i32> %tmp4
}

define <2 x i64> @uabdl2_2d(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: uabdl2_2d:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d0, [x0, #8]
; CHECK-SD-NEXT:    ldr d1, [x1, #8]
; CHECK-SD-NEXT:    uabdl.2d v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabdl2_2d:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q0, [x0]
; CHECK-GI-NEXT:    ldr q1, [x1]
; CHECK-GI-NEXT:    uabdl2.2d v0, v0, v1
; CHECK-GI-NEXT:    ret
  %load1 = load <4 x i32>, ptr %A
  %load2 = load <4 x i32>, ptr %B
  %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
  ret <2 x i64> %tmp4
}

declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)

define i16 @uabd16b_rdx(ptr %a, ptr %b) {
; CHECK-SD-LABEL: uabd16b_rdx:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x0]
; CHECK-SD-NEXT:    ldr q1, [x1]
; CHECK-SD-NEXT:    uabd.16b v0, v0, v1
; CHECK-SD-NEXT:    uaddlv.16b h0, v0
; CHECK-SD-NEXT:    fmov w0, s0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabd16b_rdx:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    movi.2d v0, #0000000000000000
; CHECK-GI-NEXT:    usubl.8h v3, v1, v2
; CHECK-GI-NEXT:    usubl2.8h v1, v1, v2
; CHECK-GI-NEXT:    neg.8h v2, v3
; CHECK-GI-NEXT:    neg.8h v4, v1
; CHECK-GI-NEXT:    cmgt.8h v5, v0, v3
; CHECK-GI-NEXT:    cmgt.8h v0, v0, v1
; CHECK-GI-NEXT:    bif.16b v2, v3, v5
; CHECK-GI-NEXT:    bsl.16b v0, v4, v1
; CHECK-GI-NEXT:    add.8h v0, v2, v0
; CHECK-GI-NEXT:    addv.8h h0, v0
; CHECK-GI-NEXT:    fmov w0, s0
; CHECK-GI-NEXT:    ret
  %aload = load <16 x i8>, ptr %a, align 1
  %bload = load <16 x i8>, ptr %b, align 1
  %aext = zext <16 x i8> %aload to <16 x i16>
  %bext = zext <16 x i8> %bload to <16 x i16>
  %abdiff = sub nsw <16 x i16> %aext, %bext
  %abcmp = icmp slt <16 x i16> %abdiff, zeroinitializer
  %ababs = sub nsw <16 x i16> zeroinitializer, %abdiff
  %absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff
  %reduced_v = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %absel)
  ret i16 %reduced_v
}

define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
; CHECK-SD-LABEL: uabd16b_rdx_i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    uabdl.8h v2, v0, v1
; CHECK-SD-NEXT:    uabal2.8h v2, v0, v1
; CHECK-SD-NEXT:    uaddlv.8h s0, v2
; CHECK-SD-NEXT:    fmov w0, s0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabd16b_rdx_i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ushll.8h v3, v0, #0
; CHECK-GI-NEXT:    ushll.8h v4, v1, #0
; CHECK-GI-NEXT:    ushll2.8h v0, v0, #0
; CHECK-GI-NEXT:    ushll2.8h v1, v1, #0
; CHECK-GI-NEXT:    movi.2d v2, #0000000000000000
; CHECK-GI-NEXT:    usubl.4s v5, v3, v4
; CHECK-GI-NEXT:    usubl2.4s v3, v3, v4
; CHECK-GI-NEXT:    usubl.4s v4, v0, v1
; CHECK-GI-NEXT:    usubl2.4s v0, v0, v1
; CHECK-GI-NEXT:    neg.4s v6, v5
; CHECK-GI-NEXT:    neg.4s v7, v3
; CHECK-GI-NEXT:    cmgt.4s v1, v2, v5
; CHECK-GI-NEXT:    neg.4s v16, v4
; CHECK-GI-NEXT:    neg.4s v17, v0
; CHECK-GI-NEXT:    cmgt.4s v18, v2, v3
; CHECK-GI-NEXT:    cmgt.4s v19, v2, v4
; CHECK-GI-NEXT:    cmgt.4s v2, v2, v0
; CHECK-GI-NEXT:    bsl.16b v1, v6, v5
; CHECK-GI-NEXT:    bit.16b v3, v7, v18
; CHECK-GI-NEXT:    bit.16b v4, v16, v19
; CHECK-GI-NEXT:    bit.16b v0, v17, v2
; CHECK-GI-NEXT:    add.4s v1, v1, v3
; CHECK-GI-NEXT:    add.4s v0, v4, v0
; CHECK-GI-NEXT:    add.4s v0, v1, v0
; CHECK-GI-NEXT:    addv.4s s0, v0
; CHECK-GI-NEXT:    fmov w0, s0
; CHECK-GI-NEXT:    ret
  %aext = zext <16 x i8> %a to <16 x i32>
  %bext = zext <16 x i8> %b to <16 x i32>
  %abdiff = sub nsw <16 x i32> %aext, %bext
  %abcmp = icmp slt <16 x i32> %abdiff, zeroinitializer
  %ababs = sub nsw <16 x i32> zeroinitializer, %abdiff
  %absel = select <16 x i1> %abcmp, <16 x i32> %ababs, <16 x i32> %abdiff
  %reduced_v = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %absel)
  ret i32 %reduced_v
}

define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
; CHECK-SD-LABEL: sabd16b_rdx_i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sabdl.8h v2, v0, v1
; CHECK-SD-NEXT:    sabal2.8h v2, v0, v1
; CHECK-SD-NEXT:    uaddlv.8h s0, v2
; CHECK-SD-NEXT:    fmov w0, s0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabd16b_rdx_i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sshll.8h v3, v0, #0
; CHECK-GI-NEXT:    sshll.8h v4, v1, #0
; CHECK-GI-NEXT:    sshll2.8h v0, v0, #0
; CHECK-GI-NEXT:    sshll2.8h v1, v1, #0
; CHECK-GI-NEXT:    movi.2d v2, #0000000000000000
; CHECK-GI-NEXT:    ssubl.4s v5, v3, v4
; CHECK-GI-NEXT:    ssubl2.4s v3, v3, v4
; CHECK-GI-NEXT:    ssubl.4s v4, v0, v1
; CHECK-GI-NEXT:    ssubl2.4s v0, v0, v1
; CHECK-GI-NEXT:    neg.4s v6, v5
; CHECK-GI-NEXT:    neg.4s v7, v3
; CHECK-GI-NEXT:    cmgt.4s v1, v2, v5
; CHECK-GI-NEXT:    neg.4s v16, v4
; CHECK-GI-NEXT:    neg.4s v17, v0
; CHECK-GI-NEXT:    cmgt.4s v18, v2, v3
; CHECK-GI-NEXT:    cmgt.4s v19, v2, v4
; CHECK-GI-NEXT:    cmgt.4s v2, v2, v0
; CHECK-GI-NEXT:    bsl.16b v1, v6, v5
; CHECK-GI-NEXT:    bit.16b v3, v7, v18
; CHECK-GI-NEXT:    bit.16b v4, v16, v19
; CHECK-GI-NEXT:    bit.16b v0, v17, v2
; CHECK-GI-NEXT:    add.4s v1, v1, v3
; CHECK-GI-NEXT:    add.4s v0, v4, v0
; CHECK-GI-NEXT:    add.4s v0, v1, v0
; CHECK-GI-NEXT:    addv.4s s0, v0
; CHECK-GI-NEXT:    fmov w0, s0
; CHECK-GI-NEXT:    ret
  %aext = sext <16 x i8> %a to <16 x i32>
  %bext = sext <16 x i8> %b to <16 x i32>
  %abdiff = sub nsw <16 x i32> %aext, %bext
  %abcmp = icmp slt <16 x i32> %abdiff, zeroinitializer
  %ababs = sub nsw <16 x i32> zeroinitializer, %abdiff
  %absel = select <16 x i1> %abcmp, <16 x i32> %ababs, <16 x i32> %abdiff
  %reduced_v = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %absel)
  ret i32 %reduced_v
}


declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)

define i32 @uabd8h_rdx(ptr %a, ptr %b) {
; CHECK-SD-LABEL: uabd8h_rdx:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x0]
; CHECK-SD-NEXT:    ldr q1, [x1]
; CHECK-SD-NEXT:    uabd.8h v0, v0, v1
; CHECK-SD-NEXT:    uaddlv.8h s0, v0
; CHECK-SD-NEXT:    fmov w0, s0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabd8h_rdx:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    movi.2d v0, #0000000000000000
; CHECK-GI-NEXT:    usubl.4s v3, v1, v2
; CHECK-GI-NEXT:    usubl2.4s v1, v1, v2
; CHECK-GI-NEXT:    neg.4s v2, v3
; CHECK-GI-NEXT:    neg.4s v4, v1
; CHECK-GI-NEXT:    cmgt.4s v5, v0, v3
; CHECK-GI-NEXT:    cmgt.4s v0, v0, v1
; CHECK-GI-NEXT:    bif.16b v2, v3, v5
; CHECK-GI-NEXT:    bsl.16b v0, v4, v1
; CHECK-GI-NEXT:    add.4s v0, v2, v0
; CHECK-GI-NEXT:    addv.4s s0, v0
; CHECK-GI-NEXT:    fmov w0, s0
; CHECK-GI-NEXT:    ret
  %aload = load <8 x i16>, ptr %a, align 1
  %bload = load <8 x i16>, ptr %b, align 1
  %aext = zext <8 x i16> %aload to <8 x i32>
  %bext = zext <8 x i16> %bload to <8 x i32>
  %abdiff = sub nsw <8 x i32> %aext, %bext
  %abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer
  %ababs = sub nsw <8 x i32> zeroinitializer, %abdiff
  %absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff
  %reduced_v = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %absel)
  ret i32 %reduced_v
}

define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
; CHECK-SD-LABEL: sabd8h_rdx:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sabd.8h v0, v0, v1
; CHECK-SD-NEXT:    uaddlv.8h s0, v0
; CHECK-SD-NEXT:    fmov w0, s0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabd8h_rdx:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ssubl.4s v3, v0, v1
; CHECK-GI-NEXT:    ssubl2.4s v0, v0, v1
; CHECK-GI-NEXT:    movi.2d v2, #0000000000000000
; CHECK-GI-NEXT:    neg.4s v1, v3
; CHECK-GI-NEXT:    neg.4s v4, v0
; CHECK-GI-NEXT:    cmgt.4s v5, v2, v3
; CHECK-GI-NEXT:    cmgt.4s v2, v2, v0
; CHECK-GI-NEXT:    bif.16b v1, v3, v5
; CHECK-GI-NEXT:    bit.16b v0, v4, v2
; CHECK-GI-NEXT:    add.4s v0, v1, v0
; CHECK-GI-NEXT:    addv.4s s0, v0
; CHECK-GI-NEXT:    fmov w0, s0
; CHECK-GI-NEXT:    ret
  %aext = sext <8 x i16> %a to <8 x i32>
  %bext = sext <8 x i16> %b to <8 x i32>
  %abdiff = sub nsw <8 x i32> %aext, %bext
  %abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer
  %ababs = sub nsw <8 x i32> zeroinitializer, %abdiff
  %absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff
  %reduced_v = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %absel)
  ret i32 %reduced_v
}

define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
; CHECK-SD-LABEL: uabdl4s_rdx_i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    uabdl.4s v0, v0, v1
; CHECK-SD-NEXT:    addv.4s s0, v0
; CHECK-SD-NEXT:    fmov w0, s0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabdl4s_rdx_i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    usubl.4s v0, v0, v1
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.4s v2, v0
; CHECK-GI-NEXT:    cmgt.4s v1, v1, v0
; CHECK-GI-NEXT:    bit.16b v0, v2, v1
; CHECK-GI-NEXT:    addv.4s s0, v0
; CHECK-GI-NEXT:    fmov w0, s0
; CHECK-GI-NEXT:    ret
  %aext = zext <4 x i16> %a to <4 x i32>
  %bext = zext <4 x i16> %b to <4 x i32>
  %abdiff = sub nsw <4 x i32> %aext, %bext
  %abcmp = icmp slt <4 x i32> %abdiff, zeroinitializer
  %ababs = sub nsw <4 x i32> zeroinitializer, %abdiff
  %absel = select <4 x i1> %abcmp, <4 x i32> %ababs, <4 x i32> %abdiff
  %reduced_v = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %absel)
  ret i32 %reduced_v
}

declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)

define i64 @uabd4s_rdx(ptr %a, ptr %b, i32 %h) {
; CHECK-SD-LABEL: uabd4s_rdx:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x0]
; CHECK-SD-NEXT:    ldr q1, [x1]
; CHECK-SD-NEXT:    uabd.4s v0, v0, v1
; CHECK-SD-NEXT:    uaddlv.4s d0, v0
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabd4s_rdx:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    movi.2d v0, #0000000000000000
; CHECK-GI-NEXT:    usubl.2d v3, v1, v2
; CHECK-GI-NEXT:    usubl2.2d v1, v1, v2
; CHECK-GI-NEXT:    neg.2d v2, v3
; CHECK-GI-NEXT:    neg.2d v4, v1
; CHECK-GI-NEXT:    cmgt.2d v5, v0, v3
; CHECK-GI-NEXT:    cmgt.2d v0, v0, v1
; CHECK-GI-NEXT:    bif.16b v2, v3, v5
; CHECK-GI-NEXT:    bsl.16b v0, v4, v1
; CHECK-GI-NEXT:    add.2d v0, v2, v0
; CHECK-GI-NEXT:    addp.2d d0, v0
; CHECK-GI-NEXT:    fmov x0, d0
; CHECK-GI-NEXT:    ret
  %aload = load <4 x i32>, ptr %a, align 1
  %bload = load <4 x i32>, ptr %b, align 1
  %aext = zext <4 x i32> %aload to <4 x i64>
  %bext = zext <4 x i32> %bload to <4 x i64>
  %abdiff = sub nsw <4 x i64> %aext, %bext
  %abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer
  %ababs = sub nsw <4 x i64> zeroinitializer, %abdiff
  %absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff
  %reduced_v = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %absel)
  ret i64 %reduced_v
}

define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
; CHECK-SD-LABEL: sabd4s_rdx:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sabd.4s v0, v0, v1
; CHECK-SD-NEXT:    uaddlv.4s d0, v0
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabd4s_rdx:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ssubl.2d v3, v0, v1
; CHECK-GI-NEXT:    ssubl2.2d v0, v0, v1
; CHECK-GI-NEXT:    movi.2d v2, #0000000000000000
; CHECK-GI-NEXT:    neg.2d v1, v3
; CHECK-GI-NEXT:    neg.2d v4, v0
; CHECK-GI-NEXT:    cmgt.2d v5, v2, v3
; CHECK-GI-NEXT:    cmgt.2d v2, v2, v0
; CHECK-GI-NEXT:    bif.16b v1, v3, v5
; CHECK-GI-NEXT:    bit.16b v0, v4, v2
; CHECK-GI-NEXT:    add.2d v0, v1, v0
; CHECK-GI-NEXT:    addp.2d d0, v0
; CHECK-GI-NEXT:    fmov x0, d0
; CHECK-GI-NEXT:    ret
  %aext = sext <4 x i32> %a to <4 x i64>
  %bext = sext <4 x i32> %b to <4 x i64>
  %abdiff = sub nsw <4 x i64> %aext, %bext
  %abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer
  %ababs = sub nsw <4 x i64> zeroinitializer, %abdiff
  %absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff
  %reduced_v = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %absel)
  ret i64 %reduced_v
}

define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
; CHECK-SD-LABEL: uabdl2d_rdx_i64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    uabdl.2d v0, v0, v1
; CHECK-SD-NEXT:    addp.2d d0, v0
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabdl2d_rdx_i64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    usubl.2d v0, v0, v1
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.2d v2, v0
; CHECK-GI-NEXT:    cmgt.2d v1, v1, v0
; CHECK-GI-NEXT:    bit.16b v0, v2, v1
; CHECK-GI-NEXT:    addp.2d d0, v0
; CHECK-GI-NEXT:    fmov x0, d0
; CHECK-GI-NEXT:    ret
  %aext = zext <2 x i32> %a to <2 x i64>
  %bext = zext <2 x i32> %b to <2 x i64>
  %abdiff = sub nsw <2 x i64> %aext, %bext
  %abcmp = icmp slt <2 x i64> %abdiff, zeroinitializer
  %ababs = sub nsw <2 x i64> zeroinitializer, %abdiff
  %absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %abdiff
  %reduced_v = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %absel)
  ret i64 %reduced_v
}

define <2 x float> @fabd_2s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: fabd_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    fabd.2s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x float>, ptr %A
  %tmp2 = load <2 x float>, ptr %B
  %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
  ret <2 x float> %tmp3
}

define <4 x float> @fabd_4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: fabd_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    fabd.4s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x float>, ptr %A
  %tmp2 = load <4 x float>, ptr %B
  %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
  ret <4 x float> %tmp3
}

define <2 x double> @fabd_2d(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: fabd_2d:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    fabd.2d v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x double>, ptr %A
  %tmp2 = load <2 x double>, ptr %B
  %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
  ret <2 x double> %tmp3
}

declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>) nounwind readnone
declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>) nounwind readnone
declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) nounwind readnone

define <2 x float> @fabd_2s_from_fsub_fabs(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: fabd_2s_from_fsub_fabs:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    fabd.2s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x float>, ptr %A
  %tmp2 = load <2 x float>, ptr %B
  %sub = fsub <2 x float> %tmp1, %tmp2
  %abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %sub)
  ret <2 x float> %abs
}

define <4 x float> @fabd_4s_from_fsub_fabs(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: fabd_4s_from_fsub_fabs:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    fabd.4s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x float>, ptr %A
  %tmp2 = load <4 x float>, ptr %B
  %sub = fsub <4 x float> %tmp1, %tmp2
  %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %sub)
  ret <4 x float> %abs
}

define <2 x double> @fabd_2d_from_fsub_fabs(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: fabd_2d_from_fsub_fabs:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    fabd.2d v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x double>, ptr %A
  %tmp2 = load <2 x double>, ptr %B
  %sub = fsub <2 x double> %tmp1, %tmp2
  %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %sub)
  ret <2 x double> %abs
}

declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone

define <8 x i8> @sabd_8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabd_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    sabd.8b v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  ret <8 x i8> %tmp3
}

define <16 x i8> @sabd_16b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabd_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    sabd.16b v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp2 = load <16 x i8>, ptr %B
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
  ret <16 x i8> %tmp3
}

define <4 x i16> @sabd_4h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabd_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    sabd.4h v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  ret <4 x i16> %tmp3
}

define <8 x i16> @sabd_8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabd_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    sabd.8h v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp2 = load <8 x i16>, ptr %B
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
  ret <8 x i16> %tmp3
}

define <2 x i32> @sabd_2s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabd_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    sabd.2s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  ret <2 x i32> %tmp3
}

define <4 x i32> @sabd_4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabd_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    sabd.4s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp2 = load <4 x i32>, ptr %B
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
  ret <4 x i32> %tmp3
}

declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone

define <8 x i8> @uabd_8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabd_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uabd.8b v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  ret <8 x i8> %tmp3
}

define <16 x i8> @uabd_16b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabd_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    uabd.16b v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp2 = load <16 x i8>, ptr %B
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
  ret <16 x i8> %tmp3
}

define <4 x i16> @uabd_4h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabd_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uabd.4h v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  ret <4 x i16> %tmp3
}

define <8 x i16> @uabd_8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabd_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    uabd.8h v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp2 = load <8 x i16>, ptr %B
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
  ret <8 x i16> %tmp3
}

define <2 x i32> @uabd_2s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabd_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uabd.2s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  ret <2 x i32> %tmp3
}

define <4 x i32> @uabd_4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabd_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ldr q1, [x1]
; CHECK-NEXT:    uabd.4s v0, v0, v1
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp2 = load <4 x i32>, ptr %B
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
  ret <4 x i32> %tmp3
}

declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone

define <8 x i8> @sqabs_8b(ptr %A) nounwind {
; CHECK-LABEL: sqabs_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    sqabs.8b v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8> %tmp1)
  ret <8 x i8> %tmp3
}

define <16 x i8> @sqabs_16b(ptr %A) nounwind {
; CHECK-LABEL: sqabs_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    sqabs.16b v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8> %tmp1)
  ret <16 x i8> %tmp3
}

define <4 x i16> @sqabs_4h(ptr %A) nounwind {
; CHECK-LABEL: sqabs_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    sqabs.4h v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16> %tmp1)
  ret <4 x i16> %tmp3
}

define <8 x i16> @sqabs_8h(ptr %A) nounwind {
; CHECK-LABEL: sqabs_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    sqabs.8h v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16> %tmp1)
  ret <8 x i16> %tmp3
}

define <2 x i32> @sqabs_2s(ptr %A) nounwind {
; CHECK-LABEL: sqabs_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    sqabs.2s v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32> %tmp1)
  ret <2 x i32> %tmp3
}

define <4 x i32> @sqabs_4s(ptr %A) nounwind {
; CHECK-LABEL: sqabs_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    sqabs.4s v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32> %tmp1)
  ret <4 x i32> %tmp3
}

declare <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32>) nounwind readnone

define <8 x i8> @sqneg_8b(ptr %A) nounwind {
; CHECK-LABEL: sqneg_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    sqneg.8b v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8> %tmp1)
  ret <8 x i8> %tmp3
}

define <16 x i8> @sqneg_16b(ptr %A) nounwind {
; CHECK-LABEL: sqneg_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    sqneg.16b v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8> %tmp1)
  ret <16 x i8> %tmp3
}

define <4 x i16> @sqneg_4h(ptr %A) nounwind {
; CHECK-LABEL: sqneg_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    sqneg.4h v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16> %tmp1)
  ret <4 x i16> %tmp3
}

define <8 x i16> @sqneg_8h(ptr %A) nounwind {
; CHECK-LABEL: sqneg_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    sqneg.8h v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %tmp1)
  ret <8 x i16> %tmp3
}

define <2 x i32> @sqneg_2s(ptr %A) nounwind {
; CHECK-LABEL: sqneg_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    sqneg.2s v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32> %tmp1)
  ret <2 x i32> %tmp3
}

define <4 x i32> @sqneg_4s(ptr %A) nounwind {
; CHECK-LABEL: sqneg_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    sqneg.4s v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32> %tmp1)
  ret <4 x i32> %tmp3
}

declare <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32>) nounwind readnone

define <8 x i8> @abs_8b(ptr %A) nounwind {
; CHECK-LABEL: abs_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    abs.8b v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8> %tmp1)
  ret <8 x i8> %tmp3
}

define <16 x i8> @abs_16b(ptr %A) nounwind {
; CHECK-LABEL: abs_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    abs.16b v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8> %tmp1)
  ret <16 x i8> %tmp3
}

define <4 x i16> @abs_4h(ptr %A) nounwind {
; CHECK-LABEL: abs_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    abs.4h v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> %tmp1)
  ret <4 x i16> %tmp3
}

define <8 x i16> @abs_8h(ptr %A) nounwind {
; CHECK-LABEL: abs_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    abs.8h v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> %tmp1)
  ret <8 x i16> %tmp3
}

define <2 x i32> @abs_2s(ptr %A) nounwind {
; CHECK-LABEL: abs_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    abs.2s v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32> %tmp1)
  ret <2 x i32> %tmp3
}

define <4 x i32> @abs_4s(ptr %A) nounwind {
; CHECK-LABEL: abs_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    abs.4s v0, v0
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32> %tmp1)
  ret <4 x i32> %tmp3
}

define <1 x i64> @abs_1d(<1 x i64> %A) nounwind {
; CHECK-LABEL: abs_1d:
; CHECK:       // %bb.0:
; CHECK-NEXT:    abs d0, d0
; CHECK-NEXT:    ret
  %abs = call <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64> %A)
  ret <1 x i64> %abs
}

define i64 @abs_1d_honestly(i64 %A) nounwind {
; CHECK-LABEL: abs_1d_honestly:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    abs d0, d0
; CHECK-NEXT:    fmov x0, d0
; CHECK-NEXT:    ret
  %abs = call i64 @llvm.aarch64.neon.abs.i64(i64 %A)
  ret i64 %abs
}

declare <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8>) nounwind readnone
declare <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8>) nounwind readnone
declare <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16>) nounwind readnone
declare <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32>) nounwind readnone
declare <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64>) nounwind readnone
declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone

define <8 x i16> @sabal8h(ptr %A, ptr %B,  ptr %C) nounwind {
; CHECK-LABEL: sabal8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    sabal.8h v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = load <8 x i16>, ptr %C
  %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
  %tmp5 = add <8 x i16> %tmp3, %tmp4.1
  ret <8 x i16> %tmp5
}

define <4 x i32> @sabal4s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: sabal4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    sabal.4s v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = load <4 x i32>, ptr %C
  %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
  %tmp5 = add <4 x i32> %tmp3, %tmp4.1
  ret <4 x i32> %tmp5
}

define <2 x i64> @sabal2d(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: sabal2d:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    sabal.2d v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = load <2 x i64>, ptr %C
  %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
  %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64>
  %tmp5 = add <2 x i64> %tmp3, %tmp4.1
  ret <2 x i64> %tmp5
}

define <8 x i16> @sabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-SD-LABEL: sabal2_8h:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x2]
; CHECK-SD-NEXT:    ldr d1, [x0, #8]
; CHECK-SD-NEXT:    ldr d2, [x1, #8]
; CHECK-SD-NEXT:    sabal.8h v0, v1, v2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabal2_8h:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    ldr q0, [x2]
; CHECK-GI-NEXT:    sabal2.8h v0, v1, v2
; CHECK-GI-NEXT:    ret
  %load1 = load <16 x i8>, ptr %A
  %load2 = load <16 x i8>, ptr %B
  %tmp3 = load <8 x i16>, ptr %C
  %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
  %tmp5 = add <8 x i16> %tmp3, %tmp4.1
  ret <8 x i16> %tmp5
}

define <4 x i32> @sabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-SD-LABEL: sabal2_4s:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x2]
; CHECK-SD-NEXT:    ldr d1, [x0, #8]
; CHECK-SD-NEXT:    ldr d2, [x1, #8]
; CHECK-SD-NEXT:    sabal.4s v0, v1, v2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabal2_4s:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    ldr q0, [x2]
; CHECK-GI-NEXT:    sabal2.4s v0, v1, v2
; CHECK-GI-NEXT:    ret
  %load1 = load <8 x i16>, ptr %A
  %load2 = load <8 x i16>, ptr %B
  %tmp3 = load <4 x i32>, ptr %C
  %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
  %tmp5 = add <4 x i32> %tmp3, %tmp4.1
  ret <4 x i32> %tmp5
}

define <2 x i64> @sabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-SD-LABEL: sabal2_2d:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x2]
; CHECK-SD-NEXT:    ldr d1, [x0, #8]
; CHECK-SD-NEXT:    ldr d2, [x1, #8]
; CHECK-SD-NEXT:    sabal.2d v0, v1, v2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabal2_2d:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    ldr q0, [x2]
; CHECK-GI-NEXT:    sabal2.2d v0, v1, v2
; CHECK-GI-NEXT:    ret
  %load1 = load <4 x i32>, ptr %A
  %load2 = load <4 x i32>, ptr %B
  %tmp3 = load <2 x i64>, ptr %C
  %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
  %tmp5 = add <2 x i64> %tmp3, %tmp4.1
  ret <2 x i64> %tmp5
}

define <8 x i16> @uabal8h(ptr %A, ptr %B,  ptr %C) nounwind {
; CHECK-LABEL: uabal8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    uabal.8h v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = load <8 x i16>, ptr %C
  %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
  %tmp5 = add <8 x i16> %tmp3, %tmp4.1
  ret <8 x i16> %tmp5
}

define <4 x i32> @uabal4s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uabal4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    uabal.4s v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = load <4 x i32>, ptr %C
  %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
  %tmp5 = add <4 x i32> %tmp3, %tmp4.1
  ret <4 x i32> %tmp5
}

define <2 x i64> @uabal2d(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uabal2d:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    uabal.2d v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = load <2 x i64>, ptr %C
  %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
  %tmp5 = add <2 x i64> %tmp3, %tmp4.1
  ret <2 x i64> %tmp5
}

define <8 x i16> @uabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-SD-LABEL: uabal2_8h:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x2]
; CHECK-SD-NEXT:    ldr d1, [x0, #8]
; CHECK-SD-NEXT:    ldr d2, [x1, #8]
; CHECK-SD-NEXT:    uabal.8h v0, v1, v2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabal2_8h:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    ldr q0, [x2]
; CHECK-GI-NEXT:    uabal2.8h v0, v1, v2
; CHECK-GI-NEXT:    ret
  %load1 = load <16 x i8>, ptr %A
  %load2 = load <16 x i8>, ptr %B
  %tmp3 = load <8 x i16>, ptr %C
  %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
  %tmp5 = add <8 x i16> %tmp3, %tmp4.1
  ret <8 x i16> %tmp5
}

define <4 x i32> @uabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-SD-LABEL: uabal2_4s:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x2]
; CHECK-SD-NEXT:    ldr d1, [x0, #8]
; CHECK-SD-NEXT:    ldr d2, [x1, #8]
; CHECK-SD-NEXT:    uabal.4s v0, v1, v2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabal2_4s:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    ldr q0, [x2]
; CHECK-GI-NEXT:    uabal2.4s v0, v1, v2
; CHECK-GI-NEXT:    ret
  %load1 = load <8 x i16>, ptr %A
  %load2 = load <8 x i16>, ptr %B
  %tmp3 = load <4 x i32>, ptr %C
  %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
  %tmp5 = add <4 x i32> %tmp3, %tmp4.1
  ret <4 x i32> %tmp5
}

define <2 x i64> @uabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-SD-LABEL: uabal2_2d:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr q0, [x2]
; CHECK-SD-NEXT:    ldr d1, [x0, #8]
; CHECK-SD-NEXT:    ldr d2, [x1, #8]
; CHECK-SD-NEXT:    uabal.2d v0, v1, v2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabal2_2d:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ldr q1, [x0]
; CHECK-GI-NEXT:    ldr q2, [x1]
; CHECK-GI-NEXT:    ldr q0, [x2]
; CHECK-GI-NEXT:    uabal2.2d v0, v1, v2
; CHECK-GI-NEXT:    ret
  %load1 = load <4 x i32>, ptr %A
  %load2 = load <4 x i32>, ptr %B
  %tmp3 = load <2 x i64>, ptr %C
  %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
  %tmp5 = add <2 x i64> %tmp3, %tmp4.1
  ret <2 x i64> %tmp5
}

define <8 x i8> @saba_8b(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: saba_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr d0, [x2]
; CHECK-NEXT:    saba.8b v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4 = load <8 x i8>, ptr %C
  %tmp5 = add <8 x i8> %tmp3, %tmp4
  ret <8 x i8> %tmp5
}

define <16 x i8> @saba_16b(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: saba_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q1, [x0]
; CHECK-NEXT:    ldr q2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    saba.16b v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp2 = load <16 x i8>, ptr %B
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
  %tmp4 = load <16 x i8>, ptr %C
  %tmp5 = add <16 x i8> %tmp3, %tmp4
  ret <16 x i8> %tmp5
}

define <4 x i16> @saba_4h(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: saba_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr d0, [x2]
; CHECK-NEXT:    saba.4h v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4 = load <4 x i16>, ptr %C
  %tmp5 = add <4 x i16> %tmp3, %tmp4
  ret <4 x i16> %tmp5
}

define <8 x i16> @saba_8h(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: saba_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q1, [x0]
; CHECK-NEXT:    ldr q2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    saba.8h v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp2 = load <8 x i16>, ptr %B
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
  %tmp4 = load <8 x i16>, ptr %C
  %tmp5 = add <8 x i16> %tmp3, %tmp4
  ret <8 x i16> %tmp5
}

define <2 x i32> @saba_2s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: saba_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr d0, [x2]
; CHECK-NEXT:    saba.2s v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4 = load <2 x i32>, ptr %C
  %tmp5 = add <2 x i32> %tmp3, %tmp4
  ret <2 x i32> %tmp5
}

define <4 x i32> @saba_4s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: saba_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q1, [x0]
; CHECK-NEXT:    ldr q2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    saba.4s v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp2 = load <4 x i32>, ptr %B
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
  %tmp4 = load <4 x i32>, ptr %C
  %tmp5 = add <4 x i32> %tmp3, %tmp4
  ret <4 x i32> %tmp5
}

define <8 x i8> @uaba_8b(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uaba_8b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr d0, [x2]
; CHECK-NEXT:    uaba.8b v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i8>, ptr %A
  %tmp2 = load <8 x i8>, ptr %B
  %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
  %tmp4 = load <8 x i8>, ptr %C
  %tmp5 = add <8 x i8> %tmp3, %tmp4
  ret <8 x i8> %tmp5
}

define <16 x i8> @uaba_16b(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uaba_16b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q1, [x0]
; CHECK-NEXT:    ldr q2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    uaba.16b v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <16 x i8>, ptr %A
  %tmp2 = load <16 x i8>, ptr %B
  %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
  %tmp4 = load <16 x i8>, ptr %C
  %tmp5 = add <16 x i8> %tmp3, %tmp4
  ret <16 x i8> %tmp5
}

define <4 x i16> @uaba_4h(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uaba_4h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr d0, [x2]
; CHECK-NEXT:    uaba.4h v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i16>, ptr %A
  %tmp2 = load <4 x i16>, ptr %B
  %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
  %tmp4 = load <4 x i16>, ptr %C
  %tmp5 = add <4 x i16> %tmp3, %tmp4
  ret <4 x i16> %tmp5
}

define <8 x i16> @uaba_8h(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uaba_8h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q1, [x0]
; CHECK-NEXT:    ldr q2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    uaba.8h v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <8 x i16>, ptr %A
  %tmp2 = load <8 x i16>, ptr %B
  %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
  %tmp4 = load <8 x i16>, ptr %C
  %tmp5 = add <8 x i16> %tmp3, %tmp4
  ret <8 x i16> %tmp5
}

define <2 x i32> @uaba_2s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uaba_2s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d1, [x0]
; CHECK-NEXT:    ldr d2, [x1]
; CHECK-NEXT:    ldr d0, [x2]
; CHECK-NEXT:    uaba.2s v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <2 x i32>, ptr %A
  %tmp2 = load <2 x i32>, ptr %B
  %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
  %tmp4 = load <2 x i32>, ptr %C
  %tmp5 = add <2 x i32> %tmp3, %tmp4
  ret <2 x i32> %tmp5
}

define <4 x i32> @uaba_4s(ptr %A, ptr %B, ptr %C) nounwind {
; CHECK-LABEL: uaba_4s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q1, [x0]
; CHECK-NEXT:    ldr q2, [x1]
; CHECK-NEXT:    ldr q0, [x2]
; CHECK-NEXT:    uaba.4s v0, v1, v2
; CHECK-NEXT:    ret
  %tmp1 = load <4 x i32>, ptr %A
  %tmp2 = load <4 x i32>, ptr %B
  %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
  %tmp4 = load <4 x i32>, ptr %C
  %tmp5 = add <4 x i32> %tmp3, %tmp4
  ret <4 x i32> %tmp5
}

; Scalar FABD
define float @fabds(float %a, float %b) nounwind {
; CHECK-LABEL: fabds:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fabd s0, s0, s1
; CHECK-NEXT:    ret
  %vabd.i = tail call float @llvm.aarch64.sisd.fabd.f32(float %a, float %b) nounwind
  ret float %vabd.i
}

define double @fabdd(double %a, double %b) nounwind {
; CHECK-LABEL: fabdd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fabd d0, d0, d1
; CHECK-NEXT:    ret
  %vabd.i = tail call double @llvm.aarch64.sisd.fabd.f64(double %a, double %b) nounwind
  ret double %vabd.i
}

declare double @llvm.aarch64.sisd.fabd.f64(double, double) nounwind readnone
declare float @llvm.aarch64.sisd.fabd.f32(float, float) nounwind readnone

define float @fabds_from_fsub_fabs(float %a, float %b) nounwind {
; CHECK-LABEL: fabds_from_fsub_fabs:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fabd s0, s0, s1
; CHECK-NEXT:    ret
  %sub = fsub float %a, %b
  %abs = tail call float @llvm.fabs.f32(float %sub)
  ret float %abs
}

define double @fabdd_from_fsub_fabs(double %a, double %b) nounwind {
; CHECK-LABEL: fabdd_from_fsub_fabs:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fabd d0, d0, d1
; CHECK-NEXT:    ret
  %sub = fsub double %a, %b
  %abs = tail call double @llvm.fabs.f64(double %sub)
  ret double %abs
}

declare float @llvm.fabs.f32(float) nounwind readnone
declare double @llvm.fabs.f64(double) nounwind readnone

define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-LABEL: uabdl_from_extract_dup:
; CHECK:       // %bb.0:
; CHECK-NEXT:    dup.2s v1, w0
; CHECK-NEXT:    uabdl.2d v0, v0, v1
; CHECK-NEXT:    ret
  %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
  %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
  %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
  %res = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
  %res1 = zext <2 x i32> %res to <2 x i64>
  ret <2 x i64> %res1
}

define <2 x i64> @uabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-SD-LABEL: uabdl2_from_extract_dup:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    dup.4s v1, w0
; CHECK-SD-NEXT:    uabdl2.2d v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabdl2_from_extract_dup:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    dup.2s v1, w0
; CHECK-GI-NEXT:    mov d0, v0[1]
; CHECK-GI-NEXT:    uabdl.2d v0, v0, v1
; CHECK-GI-NEXT:    ret
  %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
  %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
  %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %res = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
  %res1 = zext <2 x i32> %res to <2 x i64>
  ret <2 x i64> %res1
}

define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-LABEL: sabdl_from_extract_dup:
; CHECK:       // %bb.0:
; CHECK-NEXT:    dup.2s v1, w0
; CHECK-NEXT:    sabdl.2d v0, v0, v1
; CHECK-NEXT:    ret
  %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
  %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
  %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
  %res = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
  %res1 = zext <2 x i32> %res to <2 x i64>
  ret <2 x i64> %res1
}

define <2 x i64> @sabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-SD-LABEL: sabdl2_from_extract_dup:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    dup.4s v1, w0
; CHECK-SD-NEXT:    sabdl2.2d v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sabdl2_from_extract_dup:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    dup.2s v1, w0
; CHECK-GI-NEXT:    mov d0, v0[1]
; CHECK-GI-NEXT:    sabdl.2d v0, v0, v1
; CHECK-GI-NEXT:    ret
  %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
  %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
  %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
  %res = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
  %res1 = zext <2 x i32> %res to <2 x i64>
  ret <2 x i64> %res1
}

define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
; CHECK-SD-LABEL: abspattern1:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.2s v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern1:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.2s v2, v0
; CHECK-GI-NEXT:    cmge.2s v1, v0, v1
; CHECK-GI-NEXT:    bif.8b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <2 x i32> zeroinitializer, %a
  %b = icmp sge <2 x i32> %a, zeroinitializer
  %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
  ret <2 x i32> %abs
}

; For GlobalISel, this generates terrible code until we can pattern match this to abs.
define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
; CHECK-SD-LABEL: abspattern2:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.4h v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern2:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.4h v2, v0
; CHECK-GI-NEXT:    cmgt.4h v1, v0, v1
; CHECK-GI-NEXT:    bif.8b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <4 x i16> zeroinitializer, %a
  %b = icmp sgt <4 x i16> %a, zeroinitializer
  %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
  ret <4 x i16> %abs
}

define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
; CHECK-SD-LABEL: abspattern3:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.8b v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern3:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.8b v2, v0
; CHECK-GI-NEXT:    cmgt.8b v1, v1, v0
; CHECK-GI-NEXT:    bit.8b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <8 x i8> zeroinitializer, %a
  %b = icmp slt <8 x i8> %a, zeroinitializer
  %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
  ret <8 x i8> %abs
}

define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
; CHECK-SD-LABEL: abspattern4:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.4s v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern4:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.4s v2, v0
; CHECK-GI-NEXT:    cmge.4s v1, v0, v1
; CHECK-GI-NEXT:    bif.16b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <4 x i32> zeroinitializer, %a
  %b = icmp sge <4 x i32> %a, zeroinitializer
  %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
  ret <4 x i32> %abs
}

define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
; CHECK-SD-LABEL: abspattern5:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.8h v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern5:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.8h v2, v0
; CHECK-GI-NEXT:    cmgt.8h v1, v0, v1
; CHECK-GI-NEXT:    bif.16b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <8 x i16> zeroinitializer, %a
  %b = icmp sgt <8 x i16> %a, zeroinitializer
  %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
  ret <8 x i16> %abs
}

define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
; CHECK-SD-LABEL: abspattern6:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.16b v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern6:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.16b v2, v0
; CHECK-GI-NEXT:    cmgt.16b v1, v1, v0
; CHECK-GI-NEXT:    bit.16b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <16 x i8> zeroinitializer, %a
  %b = icmp slt <16 x i8> %a, zeroinitializer
  %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
  ret <16 x i8> %abs
}

define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
; CHECK-SD-LABEL: abspattern7:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    abs.2d v0, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abspattern7:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.2d v2, v0
; CHECK-GI-NEXT:    cmge.2d v1, v1, v0
; CHECK-GI-NEXT:    bit.16b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %tmp1neg = sub <2 x i64> zeroinitializer, %a
  %b = icmp sle <2 x i64> %a, zeroinitializer
  %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
  ret <2 x i64> %abs
}

define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-SD-LABEL: uabd_i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sabdl.2d v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: uabd_i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    ssubl.2d v0, v0, v1
; CHECK-GI-NEXT:    movi.2d v1, #0000000000000000
; CHECK-GI-NEXT:    neg.2d v2, v0
; CHECK-GI-NEXT:    cmgt.2d v1, v1, v0
; CHECK-GI-NEXT:    bit.16b v0, v2, v1
; CHECK-GI-NEXT:    ret
  %aext = sext <2 x i32> %a to <2 x i64>
  %bext = sext <2 x i32> %b to <2 x i64>
  %abdiff = sub nsw <2 x i64> %aext, %bext
  %abcmp = icmp slt <2 x i64> %abdiff, zeroinitializer
  %ababs = sub nsw <2 x i64> zeroinitializer, %abdiff
  %absel = select <2 x i1> %abcmp, <2 x i64> %ababs, <2 x i64> %abdiff
  ret <2 x i64> %absel
}

define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: uabd_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov.d x8, v0[1]
; CHECK-NEXT:    mov.d x9, v1[1]
; CHECK-NEXT:    fmov x10, d0
; CHECK-NEXT:    fmov x11, d1
; CHECK-NEXT:    asr x12, x10, #63
; CHECK-NEXT:    asr x13, x11, #63
; CHECK-NEXT:    subs x10, x10, x11
; CHECK-NEXT:    asr x11, x8, #63
; CHECK-NEXT:    asr x14, x9, #63
; CHECK-NEXT:    sbc x12, x12, x13
; CHECK-NEXT:    subs x8, x8, x9
; CHECK-NEXT:    sbc x9, x11, x14
; CHECK-NEXT:    asr x13, x12, #63
; CHECK-NEXT:    asr x11, x9, #63
; CHECK-NEXT:    eor x10, x10, x13
; CHECK-NEXT:    eor x8, x8, x11
; CHECK-NEXT:    eor x9, x9, x11
; CHECK-NEXT:    subs x2, x8, x11
; CHECK-NEXT:    eor x8, x12, x13
; CHECK-NEXT:    sbc x3, x9, x11
; CHECK-NEXT:    subs x9, x10, x13
; CHECK-NEXT:    fmov d0, x9
; CHECK-NEXT:    sbc x1, x8, x13
; CHECK-NEXT:    mov.d v0[1], x1
; CHECK-NEXT:    fmov x0, d0
; CHECK-NEXT:    ret
  %aext = sext <2 x i64> %a to <2 x i128>
  %bext = sext <2 x i64> %b to <2 x i128>
  %abdiff = sub nsw <2 x i128> %aext, %bext
  %abcmp = icmp slt <2 x i128> %abdiff, zeroinitializer
  %ababs = sub nsw <2 x i128> zeroinitializer, %abdiff
  %absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff
  ret <2 x i128> %absel
}

define <8 x i16> @pr88784(<8 x i8> %l0, <8 x i8> %l1, <8 x i16> %l2) {
; CHECK-SD-LABEL: pr88784:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    usubl.8h v0, v0, v1
; CHECK-SD-NEXT:    cmlt.8h v1, v2, #0
; CHECK-SD-NEXT:    ssra.8h v0, v2, #15
; CHECK-SD-NEXT:    eor.16b v0, v1, v0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: pr88784:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    usubl.8h v0, v0, v1
; CHECK-GI-NEXT:    sshr.8h v1, v2, #15
; CHECK-GI-NEXT:    ssra.8h v0, v2, #15
; CHECK-GI-NEXT:    eor.16b v0, v1, v0
; CHECK-GI-NEXT:    ret
  %l4 = zext <8 x i8> %l0 to <8 x i16>
  %l5 = ashr <8 x i16> %l2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %l6 = zext <8 x i8> %l1 to <8 x i16>
  %l7 = sub <8 x i16> %l4, %l6
  %l8 = add <8 x i16> %l5, %l7
  %l9 = xor <8 x i16> %l5, %l8
  ret <8 x i16> %l9
}

define <8 x i16> @pr88784_fixed(<8 x i8> %l0, <8 x i8> %l1, <8 x i16> %l2) {
; CHECK-SD-LABEL: pr88784_fixed:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    uabdl.8h v0, v0, v1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: pr88784_fixed:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    usubl.8h v0, v0, v1
; CHECK-GI-NEXT:    sshr.8h v1, v0, #15
; CHECK-GI-NEXT:    ssra.8h v0, v0, #15
; CHECK-GI-NEXT:    eor.16b v0, v1, v0
; CHECK-GI-NEXT:    ret
  %l4 = zext <8 x i8> %l0 to <8 x i16>
  %l6 = zext <8 x i8> %l1 to <8 x i16>
  %l7 = sub <8 x i16> %l4, %l6
  %l5 = ashr <8 x i16> %l7, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %l8 = add <8 x i16> %l5, %l7
  %l9 = xor <8 x i16> %l5, %l8
  ret <8 x i16> %l9
}