; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s target triple = "aarch64" ; Expected to transform define @complex_add_v2f64( %a, %b) { ; CHECK-LABEL: complex_add_v2f64: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcadd z1.d, p0/m, z1.d, z0.d, #90 ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret entry: %a.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv2f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv2f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv2f64( %0, %1) ret %interleaved.vec } ; Expected to transform define @complex_add_v4f64( %a, %b) { ; CHECK-LABEL: complex_add_v4f64: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcadd z2.d, p0/m, z2.d, z0.d, #90 ; CHECK-NEXT: fcadd z3.d, p0/m, z3.d, z1.d, #90 ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: mov z1.d, z3.d ; CHECK-NEXT: ret entry: %a.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %0, %1) ret %interleaved.vec } ; Expected to transform define @complex_add_v8f64( %a, %b) { ; CHECK-LABEL: complex_add_v8f64: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcadd z4.d, p0/m, z4.d, z0.d, #90 ; CHECK-NEXT: fcadd z5.d, p0/m, z5.d, z1.d, #90 ; CHECK-NEXT: fcadd z6.d, p0/m, z6.d, z2.d, #90 ; CHECK-NEXT: fcadd z7.d, p0/m, z7.d, z3.d, #90 ; CHECK-NEXT: mov z0.d, z4.d ; CHECK-NEXT: mov z1.d, z5.d ; CHECK-NEXT: mov z2.d, z6.d ; CHECK-NEXT: mov z3.d, z7.d ; CHECK-NEXT: ret entry: %a.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f64( %0, %1) ret %interleaved.vec } declare { , } @llvm.experimental.vector.deinterleave2.nxv2f64() declare @llvm.experimental.vector.interleave2.nxv2f64(, ) declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() declare @llvm.experimental.vector.interleave2.nxv4f64(, ) declare { , } @llvm.experimental.vector.deinterleave2.nxv8f64() declare @llvm.experimental.vector.interleave2.nxv8f64(, )