; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s target triple = "aarch64-arm-none-eabi" ; Expected to transform define @complex_add_v4i32( %a, %b) { ; CHECK-LABEL: complex_add_v4i32: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: cadd z1.s, z1.s, z0.s, #90 ; CHECK-NEXT: mov z0.d, z1.d ; CHECK-NEXT: ret entry: %a.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i32( %0, %1) ret %interleaved.vec } ; Expected to transform define @complex_add_v8i32( %a, %b) { ; CHECK-LABEL: complex_add_v8i32: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: cadd z3.s, z3.s, z1.s, #90 ; CHECK-NEXT: cadd z2.s, z2.s, z0.s, #90 ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: mov z1.d, z3.d ; CHECK-NEXT: ret entry: %a.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i32( %0, %1) ret %interleaved.vec } ; Expected to transform define @complex_add_v16i32( %a, %b) { ; CHECK-LABEL: complex_add_v16i32: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: cadd z6.s, z6.s, z2.s, #90 ; CHECK-NEXT: cadd z4.s, z4.s, z0.s, #90 ; CHECK-NEXT: cadd z5.s, z5.s, z1.s, #90 ; CHECK-NEXT: cadd z7.s, z7.s, z3.s, #90 ; CHECK-NEXT: mov z0.d, z4.d ; CHECK-NEXT: mov z1.d, z5.d ; CHECK-NEXT: mov z2.d, z6.d ; CHECK-NEXT: mov z3.d, z7.d ; CHECK-NEXT: ret entry: %a.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16i32( %0, %1) ret %interleaved.vec } declare { , } @llvm.experimental.vector.deinterleave2.nxv4i32() declare @llvm.experimental.vector.interleave2.nxv4i32(, ) declare { , } @llvm.experimental.vector.deinterleave2.nxv8i32() declare @llvm.experimental.vector.interleave2.nxv8i32(, ) declare { , } @llvm.experimental.vector.deinterleave2.nxv16i32() declare @llvm.experimental.vector.interleave2.nxv16i32(, )