; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" ; SCALABLE INSERTED INTO SCALABLE TESTS define @vec_scalable_subvec_scalable_idx_zero_i8(* %a, * %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1b { z1.s }, p1/z, [x1] ; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h ; CHECK-NEXT: ret %vec = load , * %a %subvec = load , * %b %ins = call @llvm.vector.insert.nxv8i8.nxv4i8( %vec, %subvec, i64 0) ret %ins } define @vec_scalable_subvec_scalable_idx_nonzero_i8(* %a, * %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0] ; CHECK-NEXT: ld1b { z1.s }, p1/z, [x1] ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h ; CHECK-NEXT: ret %vec = load , * %a %subvec = load , * %b %ins = call @llvm.vector.insert.nxv8i8.nxv4i8( %vec, %subvec, i64 4) ret %ins } define @vec_scalable_subvec_scalable_idx_zero_i16(* %a, * %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p1.d ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1h { z1.d }, p1/z, [x1] ; CHECK-NEXT: uunpkhi z0.d, z0.s ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s ; CHECK-NEXT: ret %vec = load , * %a %subvec = load , * %b %ins = call @llvm.vector.insert.nxv4i16.nxv2i16( %vec, %subvec, i64 0) ret %ins } define @vec_scalable_subvec_scalable_idx_nonzero_i16(* %a, * %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p1.d ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: ld1h { z1.d }, p1/z, [x1] ; CHECK-NEXT: uunpklo z0.d, z0.s ; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s ; CHECK-NEXT: ret %vec = load , * %a %subvec = load , * %b %ins = call @llvm.vector.insert.nxv4i16.nxv2i16( %vec, %subvec, i64 2) ret %ins } ; FIXED INSERTED INTO SCALABLE TESTS define @vec_scalable_subvec_fixed_idx_zero_i8(* %a, <8 x i8>* %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ptrue p1.h, vl8 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0] ; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <8 x i8>, <8 x i8>* %b %ins = call @llvm.vector.insert.nxv8i8.v8i8( %vec, <8 x i8> %subvec, i64 0) ret %ins } define @vec_scalable_subvec_fixed_idx_nonzero_i8(* %a, <8 x i8>* %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: cnth x8 ; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: sub x8, x8, #8 ; CHECK-NEXT: mov w9, #8 // =0x8 ; CHECK-NEXT: cmp x8, #8 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: lsl x8, x8, #1 ; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0] ; CHECK-NEXT: st1h { z1.h }, p0, [sp] ; CHECK-NEXT: str q0, [x9, x8] ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] ; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <8 x i8>, <8 x i8>* %b %ins = call @llvm.vector.insert.nxv8i8.v8i8( %vec, <8 x i8> %subvec, i64 8) ret %ins } define @vec_scalable_subvec_fixed_idx_zero_i16(* %a, <4 x i16>* %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ptrue p1.s, vl4 ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0] ; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <4 x i16>, <4 x i16>* %b %ins = call @llvm.vector.insert.nxv4i16.v4i16( %vec, <4 x i16> %subvec, i64 0) ret %ins } define @vec_scalable_subvec_fixed_idx_nonzero_i16(* %a, <4 x i16>* %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: cntw x8 ; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: sub x8, x8, #4 ; CHECK-NEXT: mov w9, #4 // =0x4 ; CHECK-NEXT: cmp x8, #4 ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: lsl x8, x8, #2 ; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0] ; CHECK-NEXT: st1w { z1.s }, p0, [sp] ; CHECK-NEXT: str q0, [x9, x8] ; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] ; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <4 x i16>, <4 x i16>* %b %ins = call @llvm.vector.insert.nxv4i16.v4i16( %vec, <4 x i16> %subvec, i64 4) ret %ins } define @vec_scalable_subvec_fixed_idx_zero_i32(* %a, <2 x i32>* %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ptrue p1.d, vl2 ; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0] ; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <2 x i32>, <2 x i32>* %b %ins = call @llvm.vector.insert.nxv2i32.v2i32( %vec, <2 x i32> %subvec, i64 0) ret %ins } define @vec_scalable_subvec_fixed_idx_nonzero_i32(* %a, <2 x i32>* %b) #0 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: cntd x8 ; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: sub x8, x8, #2 ; CHECK-NEXT: mov w9, #2 // =0x2 ; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: csel x8, x8, x9, lo ; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z1.d }, p0, [sp] ; CHECK-NEXT: str q0, [x9, x8] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <2 x i32>, <2 x i32>* %b %ins = call @llvm.vector.insert.nxv2i32.v2i32( %vec, <2 x i32> %subvec, i64 2) ret %ins } define @vec_scalable_subvec_fixed_idx_nonzero_large_i32(* %a, <8 x i32>* %b) #1 { ; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_large_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: addvl sp, sp, #-1 ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p1.d, vl8 ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0] ; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: ld1w { z0.d }, p1/z, [x1] ; CHECK-NEXT: st1d { z0.d }, p0, [sp] ; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] ; CHECK-NEXT: addvl sp, sp, #1 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret %vec = load , * %a %subvec = load <8 x i32>, <8 x i32>* %b %ins = call @llvm.vector.insert.nxv2i32.v8i32( %vec, <8 x i32> %subvec, i64 8) ret %ins } declare @llvm.vector.insert.nxv8i8.nxv4i8(, , i64) declare @llvm.vector.insert.nxv4i16.nxv2i16(, , i64) declare @llvm.vector.insert.nxv8i8.v8i8(, <8 x i8>, i64) declare @llvm.vector.insert.nxv4i16.v4i16(, <4 x i16>, i64) declare @llvm.vector.insert.nxv2i32.v2i32(, <2 x i32>, i64) declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64) attributes #0 = { nounwind "target-features"="+sve" } attributes #1 = { nounwind "target-features"="+sve" vscale_range(4,4) }