; RUN: opt -S -aarch64-sve-intrinsic-opts < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" define void @pred_store_v2i8( %pred, ptr %addr) #0 { ; CHECK-LABEL: @pred_store_v2i8( ; CHECK-NEXT: store %pred, ptr %addr ; CHECK-NEXT: ret void %bitcast = bitcast %pred to %extract = tail call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8( %bitcast, i64 0) store <2 x i8> %extract, ptr %addr, align 4 ret void } define void @pred_store_v4i8( %pred, ptr %addr) #1 { ; CHECK-LABEL: @pred_store_v4i8( ; CHECK-NEXT: store %pred, ptr %addr ; CHECK-NEXT: ret void %bitcast = bitcast %pred to %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8( %bitcast, i64 0) store <4 x i8> %extract, ptr %addr, align 4 ret void } define void @pred_store_v8i8( %pred, ptr %addr) #2 { ; CHECK-LABEL: @pred_store_v8i8( ; CHECK-NEXT: store %pred, ptr %addr ; CHECK-NEXT: ret void %bitcast = bitcast %pred to %extract = tail call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %bitcast, i64 0) store <8 x i8> %extract, ptr %addr, align 4 ret void } ; Check that too small of a vscale prevents optimization define void @pred_store_neg1( %pred, ptr %addr) #0 { ; CHECK-LABEL: @pred_store_neg1( ; CHECK: call <4 x i8> @llvm.vector.extract %bitcast = bitcast %pred to %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8( %bitcast, i64 0) store <4 x i8> %extract, ptr %addr, align 4 ret void } ; Check that too large of a vscale prevents optimization define void @pred_store_neg2( %pred, ptr %addr) #2 { ; CHECK-LABEL: @pred_store_neg2( ; CHECK: call <4 x i8> @llvm.vector.extract %bitcast = bitcast %pred to %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8( %bitcast, i64 0) store <4 x i8> %extract, ptr %addr, align 4 ret void } ; Check that a non-zero index prevents optimization define void @pred_store_neg3( %pred, ptr %addr) #1 { ; CHECK-LABEL: @pred_store_neg3( ; CHECK: call <4 x i8> @llvm.vector.extract %bitcast = bitcast %pred to %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8( %bitcast, i64 4) store <4 x i8> %extract, ptr %addr, align 4 ret void } ; Check that differing vscale min/max prevents optimization define void @pred_store_neg4( %pred, ptr %addr) #3 { ; CHECK-LABEL: @pred_store_neg4( ; CHECK: call <4 x i8> @llvm.vector.extract %bitcast = bitcast %pred to %extract = tail call <4 x i8> @llvm.vector.extract.v4i8.nxv2i8( %bitcast, i64 0) store <4 x i8> %extract, ptr %addr, align 4 ret void } declare <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(, i64) declare <4 x i8> @llvm.vector.extract.v4i8.nxv2i8(, i64) declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64) attributes #0 = { "target-features"="+sve" vscale_range(1,1) } attributes #1 = { "target-features"="+sve" vscale_range(2,2) } attributes #2 = { "target-features"="+sve" vscale_range(4,4) } attributes #3 = { "target-features"="+sve" vscale_range(2,4) }