; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s ; ; SMULH ; define @smulh_i8( %a, %b) #0 { ; CHECK-LABEL: smulh_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: ret %insert = insertelement undef, i16 8, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = sext %a to %2 = sext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } define @smulh_i16( %a, %b) #0 { ; CHECK-LABEL: smulh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: ret %insert = insertelement undef, i32 16, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = sext %a to %2 = sext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } define @smulh_i32( %a, %b) #0 { ; CHECK-LABEL: smulh_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret %insert = insertelement undef, i64 32, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = sext %a to %2 = sext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } define @smulh_i64( %a, %b) #0 { ; CHECK-LABEL: smulh_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: ret %insert = insertelement undef, i128 64, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = sext %a to %2 = sext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } ; ; UMULH ; define @umulh_i8( %a, %b) #0 { ; CHECK-LABEL: umulh_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.b ; CHECK-NEXT: umulh z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: ret %insert = insertelement undef, i16 8, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = zext %a to %2 = zext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } define @umulh_i16( %a, %b) #0 { ; CHECK-LABEL: umulh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.h ; CHECK-NEXT: umulh z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: ret %insert = insertelement undef, i32 16, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = zext %a to %2 = zext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } define @umulh_i32( %a, %b) #0 { ; CHECK-LABEL: umulh_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret %insert = insertelement undef, i64 32, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = zext %a to %2 = zext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } define @umulh_i64( %a, %b) #0 { ; CHECK-LABEL: umulh_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: umulh z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: ret %insert = insertelement undef, i128 64, i64 0 %splat = shufflevector %insert, undef, zeroinitializer %1 = zext %a to %2 = zext %b to %mul = mul %1, %2 %shr = lshr %mul, %splat %tr = trunc %shr to ret %tr } attributes #0 = { "target-features"="+sve" }