# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s # Should create an additional LSL to zero the lanes as the DstReg is not unique --- | define @fmul_float_zero( %pg, %a){ %a_z = select %pg, %a, zeroinitializer %out = call @llvm.aarch64.sve.fmul.nxv4f32( %pg, %a_z, %a_z) ret %out } declare @llvm.aarch64.sve.fmul.nxv4f32(, , ) ... --- name: fmul_float_zero alignment: 4 tracksRegLiveness: true tracksDebugUserValues: true registers: [] liveins: - { reg: '$p0', virtual-reg: '' } - { reg: '$z0', virtual-reg: '' } body: | bb.0 (%ir-block.0): liveins: $p0, $z0 ; CHECK-LABEL: name: fmul_float_zero ; CHECK: liveins: $p0, $z0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit $p0, implicit $z0 { ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0 ; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0 ; CHECK-NEXT: $z0 = FMUL_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0 ; CHECK-NEXT: } ; CHECK-NEXT: RET undef $lr, implicit $z0 renamable $z0 = nnan ninf nsz arcp contract afn reassoc FMUL_ZPZZ_S_ZERO renamable $p0, killed renamable $z0, renamable $z0 RET_ReallyLR implicit $z0 ...