; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s define void @masked_scatter_nxv2i8( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2i8: ; CHECK: // %bb.0: ; CHECK-NEXT: st1b { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2i8( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2i16( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2i16( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2i32( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2i32( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2i64( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2i64( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2f16( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2f16( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2bf16( %data, %ptrs, %masks) nounwind #0 { ; CHECK-LABEL: masked_scatter_nxv2bf16: ; CHECK: // %bb.0: ; CHECK-NEXT: st1h { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2bf16( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2f32( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: st1w { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2f32( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_nxv2f64( %data, %ptrs, %masks) nounwind { ; CHECK-LABEL: masked_scatter_nxv2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: st1d { z0.d }, p0, [z1.d] ; CHECK-NEXT: ret call void @llvm.masked.scatter.nxv2f64( %data, %ptrs, i32 0, %masks) ret void } define void @masked_scatter_splat_constant_pointer ( %pg) { ; CHECK-LABEL: masked_scatter_splat_constant_pointer: ; CHECK: // %bb.0: // %vector.body ; CHECK-NEXT: punpklo p1.h, p0.b ; CHECK-NEXT: mov z0.d, #0 // =0x0 ; CHECK-NEXT: punpkhi p0.h, p0.b ; CHECK-NEXT: st1w { z0.d }, p1, [z0.d] ; CHECK-NEXT: st1w { z0.d }, p0, [z0.d] ; CHECK-NEXT: ret vector.body: call void @llvm.masked.scatter.nxv4i32.nxv4p0i32( undef, shufflevector ( insertelement ( poison, i32* null, i32 0), poison, zeroinitializer), i32 4, %pg) ret void } %i64_x3 = type { i64, i64, i64 } define void @masked_scatter_non_power_of_two_based_scaling( %data, ptr %base, %offsets, %mask) { ; CHECK-LABEL: masked_scatter_non_power_of_two_based_scaling: ; CHECK: // %bb.0: ; CHECK-NEXT: mul z1.d, z1.d, #24 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d] ; CHECK-NEXT: ret %ptrs = getelementptr inbounds %i64_x3, ptr %base, %offsets call void @llvm.masked.scatter.nxv2f64( %data, %ptrs, i32 8, %mask) ret void } %i64_x4 = type { i64, i64, i64, i64} define void @masked_scatter_non_element_type_based_scaling( %data, ptr %base, %offsets, %mask) { ; CHECK-LABEL: masked_scatter_non_element_type_based_scaling: ; CHECK: // %bb.0: ; CHECK-NEXT: lsl z1.d, z1.d, #5 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d] ; CHECK-NEXT: ret %ptrs = getelementptr inbounds %i64_x4, ptr %base, %offsets call void @llvm.masked.scatter.nxv2f64( %data, %ptrs, i32 8, %mask) ret void } declare void @llvm.masked.scatter.nxv2f16(, , i32, ) declare void @llvm.masked.scatter.nxv2bf16(, , i32, ) declare void @llvm.masked.scatter.nxv2f32(, , i32, ) declare void @llvm.masked.scatter.nxv2f64(, , i32, ) declare void @llvm.masked.scatter.nxv2i16(, , i32, ) declare void @llvm.masked.scatter.nxv2i32(, , i32, ) declare void @llvm.masked.scatter.nxv2i64(, , i32, ) declare void @llvm.masked.scatter.nxv2i8(, , i32, ) declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(, , i32, ) attributes #0 = { "target-features"="+sve,+bf16" }