; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s ; ; OR reductions ; define i1 @reduce_or_insert_subvec_into_zero( %in) { ; CHECK-LABEL: reduce_or_insert_subvec_into_zero: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: ptest p1, p0.b ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret %t = call @llvm.vector.insert.nxv16i1.nxv4i1( zeroinitializer, %in, i64 0) %res = call i1 @llvm.vector.reduce.or.nxv16i1( %t) ret i1 %res } define i1 @reduce_or_insert_subvec_into_poison( %in) { ; CHECK-LABEL: reduce_or_insert_subvec_into_poison: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: ptest p1, p0.b ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret %t = call @llvm.vector.insert.nxv16i1.nxv4i1( poison, %in, i64 0) %res = call i1 @llvm.vector.reduce.or.nxv16i1( %t) ret i1 %res } define i1 @reduce_or_insert_subvec_into_nonzero( %in, %vec) { ; CHECK-LABEL: reduce_or_insert_subvec_into_nonzero: ; CHECK: // %bb.0: ; CHECK-NEXT: punpklo p2.h, p1.b ; CHECK-NEXT: punpkhi p1.h, p1.b ; CHECK-NEXT: punpkhi p2.h, p2.b ; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: ptest p0, p0.b ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret %t = call @llvm.vector.insert.nxv16i1.nxv4i1( %vec, %in, i64 0) %res = call i1 @llvm.vector.reduce.or.nxv16i1( %t) ret i1 %res } ; ; AND reductions ; define i1 @reduce_and_insert_subvec_into_ones( %in) { ; CHECK-LABEL: reduce_and_insert_subvec_into_ones: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: nots p0.b, p1/z, p0.b ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %allones.ins = insertelement poison, i1 1, i32 0 %allones = shufflevector %allones.ins, poison, zeroinitializer %t = call @llvm.vector.insert.nxv16i1.nxv4i1( %allones, %in, i64 0) %res = call i1 @llvm.vector.reduce.and.nxv16i1( %t) ret i1 %res } define i1 @reduce_and_insert_subvec_into_poison( %in) { ; CHECK-LABEL: reduce_and_insert_subvec_into_poison: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p1.s ; CHECK-NEXT: nots p0.b, p1/z, p0.b ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %t = call @llvm.vector.insert.nxv16i1.nxv4i1( poison, %in, i64 0) %res = call i1 @llvm.vector.reduce.and.nxv16i1( %t) ret i1 %res } define i1 @reduce_and_insert_subvec_into_var( %in, %vec) { ; CHECK-LABEL: reduce_and_insert_subvec_into_var: ; CHECK: // %bb.0: ; CHECK-NEXT: punpklo p3.h, p1.b ; CHECK-NEXT: punpkhi p1.h, p1.b ; CHECK-NEXT: ptrue p2.b ; CHECK-NEXT: punpkhi p3.h, p3.b ; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h ; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b ; CHECK-NEXT: nots p0.b, p2/z, p0.b ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %t = call @llvm.vector.insert.nxv16i1.nxv4i1( %vec, %in, i64 0) %res = call i1 @llvm.vector.reduce.and.nxv16i1( %t) ret i1 %res } declare i1 @llvm.vector.reduce.and.nxv16i1() declare i1 @llvm.vector.reduce.or.nxv16i1() declare @llvm.vector.insert.nxv16i1.nxv4i1(, , i64)