; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s ; ; MUL with SPLAT ; define @mul_i16_imm( %a) { ; CHECK-LABEL: mul_i16_imm: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z1.h, #255 // =0xff ; CHECK-NEXT: mul z0.h, z0.h, z1.h ; CHECK-NEXT: ret %elt = insertelement undef, i16 255, i32 0 %splat = shufflevector %elt, undef, zeroinitializer %res = mul %a, %splat ret %res } define @mul_i16_imm_neg( %a) { ; CHECK-LABEL: mul_i16_imm_neg: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #-200 ; CHECK-NEXT: mov z1.h, w8 ; CHECK-NEXT: mul z0.h, z0.h, z1.h ; CHECK-NEXT: ret %elt = insertelement undef, i16 -200, i32 0 %splat = shufflevector %elt, undef, zeroinitializer %res = mul %a, %splat ret %res } define @mul_i32_imm( %a) { ; CHECK-LABEL: mul_i32_imm: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z1.s, #255 // =0xff ; CHECK-NEXT: mul z0.s, z0.s, z1.s ; CHECK-NEXT: ret %elt = insertelement undef, i32 255, i32 0 %splat = shufflevector %elt, undef, zeroinitializer %res = mul %a, %splat ret %res } define @mul_i32_imm_neg( %a) { ; CHECK-LABEL: mul_i32_imm_neg: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #-200 ; CHECK-NEXT: mov z1.s, w8 ; CHECK-NEXT: mul z0.s, z0.s, z1.s ; CHECK-NEXT: ret %elt = insertelement undef, i32 -200, i32 0 %splat = shufflevector %elt, undef, zeroinitializer %res = mul %a, %splat ret %res } define @mul_i64_imm( %a) { ; CHECK-LABEL: mul_i64_imm: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z1.d, #255 // =0xff ; CHECK-NEXT: mul z0.d, z0.d, z1.d ; CHECK-NEXT: ret %elt = insertelement undef, i64 255, i32 0 %splat = shufflevector %elt, undef, zeroinitializer %res = mul %a, %splat ret %res } define @mul_i64_imm_neg( %a) { ; CHECK-LABEL: mul_i64_imm_neg: ; CHECK: // %bb.0: ; CHECK-NEXT: mov x8, #-200 ; CHECK-NEXT: mov z1.d, x8 ; CHECK-NEXT: mul z0.d, z0.d, z1.d ; CHECK-NEXT: ret %elt = insertelement undef, i64 -200, i32 0 %splat = shufflevector %elt, undef, zeroinitializer %res = mul %a, %splat ret %res } ; ; MUL (vector, unpredicated) ; define @mul_i8( %a, ; CHECK-LABEL: mul_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: mul z0.b, z0.b, z1.b ; CHECK-NEXT: ret %b) { %res = mul %a, %b ret %res } define @mul_i16( %a, ; CHECK-LABEL: mul_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: mul z0.h, z0.h, z1.h ; CHECK-NEXT: ret %b) { %res = mul %a, %b ret %res } define @mul_i32( %a, ; CHECK-LABEL: mul_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: mul z0.s, z0.s, z1.s ; CHECK-NEXT: ret %b) { %res = mul %a, %b ret %res } define @mul_i64( %a, ; CHECK-LABEL: mul_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mul z0.d, z0.d, z1.d ; CHECK-NEXT: ret %b) { %res = mul %a, %b ret %res } ; ; SMULH (vector, unpredicated) ; define @smulh_i8( %a, ; CHECK-LABEL: smulh_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: smulh z0.b, z0.b, z1.b ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %res = call @llvm.aarch64.sve.smulh.u.nxv16i8( %sel, %a, %b) ret %res } define @smulh_i16( %a, ; CHECK-LABEL: smulh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: smulh z0.h, z0.h, z1.h ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %res = call @llvm.aarch64.sve.smulh.u.nxv8i16( %sel, %a, %b) ret %res } define @smulh_i32( %a, ; CHECK-LABEL: smulh_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: smulh z0.s, z0.s, z1.s ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %res = call @llvm.aarch64.sve.smulh.u.nxv4i32( %sel, %a, %b) ret %res } define @smulh_i64( %a, ; CHECK-LABEL: smulh_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: smulh z0.d, z0.d, z1.d ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %res = call @llvm.aarch64.sve.smulh.u.nxv2i64( %sel, %a, %b) ret %res } ; ; UMULH (vector, unpredicated) ; define @umulh_i8( %a, ; CHECK-LABEL: umulh_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: umulh z0.b, z0.b, z1.b ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) %res = call @llvm.aarch64.sve.umulh.u.nxv16i8( %sel, %a, %b) ret %res } define @umulh_i16( %a, ; CHECK-LABEL: umulh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: umulh z0.h, z0.h, z1.h ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) %res = call @llvm.aarch64.sve.umulh.u.nxv8i16( %sel, %a, %b) ret %res } define @umulh_i32( %a, ; CHECK-LABEL: umulh_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: umulh z0.s, z0.s, z1.s ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) %res = call @llvm.aarch64.sve.umulh.u.nxv4i32( %sel, %a, %b) ret %res } define @umulh_i64( %a, ; CHECK-LABEL: umulh_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: umulh z0.d, z0.d, z1.d ; CHECK-NEXT: ret %b) { %sel = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) %res = call @llvm.aarch64.sve.umulh.u.nxv2i64( %sel, %a, %b) ret %res } ; ; PMUL (vector, unpredicated) ; define @pmul_i8( %a, ; CHECK-LABEL: pmul_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: pmul z0.b, z0.b, z1.b ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.pmul.nxv16i8( %a, %b) ret %res } ; ; SQDMULH (vector, unpredicated) ; define @sqdmulh_i8( %a, ; CHECK-LABEL: sqdmulh_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: sqdmulh z0.b, z0.b, z1.b ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqdmulh.nxv16i8( %a, %b) ret %res } define @sqdmulh_i16( %a, ; CHECK-LABEL: sqdmulh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sqdmulh z0.h, z0.h, z1.h ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqdmulh.nxv8i16( %a, %b) ret %res } define @sqdmulh_i32( %a, ; CHECK-LABEL: sqdmulh_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sqdmulh z0.s, z0.s, z1.s ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqdmulh.nxv4i32( %a, %b) ret %res } define @sqdmulh_i64( %a, ; CHECK-LABEL: sqdmulh_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: sqdmulh z0.d, z0.d, z1.d ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqdmulh.nxv2i64( %a, %b) ret %res } ; ; SQRDMULH (vector, unpredicated) ; define @sqrdmulh_i8( %a, ; CHECK-LABEL: sqrdmulh_i8: ; CHECK: // %bb.0: ; CHECK-NEXT: sqrdmulh z0.b, z0.b, z1.b ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqrdmulh.nxv16i8( %a, %b) ret %res } define @sqrdmulh_i16( %a, ; CHECK-LABEL: sqrdmulh_i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sqrdmulh z0.h, z0.h, z1.h ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqrdmulh.nxv8i16( %a, %b) ret %res } define @sqrdmulh_i32( %a, ; CHECK-LABEL: sqrdmulh_i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sqrdmulh z0.s, z0.s, z1.s ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqrdmulh.nxv4i32( %a, %b) ret %res } define @sqrdmulh_i64( %a, ; CHECK-LABEL: sqrdmulh_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: sqrdmulh z0.d, z0.d, z1.d ; CHECK-NEXT: ret %b) { %res = call @llvm.aarch64.sve.sqrdmulh.nxv2i64( %a, %b) ret %res } declare @llvm.aarch64.sve.ptrue.nxv16i1(i32) declare @llvm.aarch64.sve.ptrue.nxv8i1(i32) declare @llvm.aarch64.sve.ptrue.nxv4i1(i32) declare @llvm.aarch64.sve.ptrue.nxv2i1(i32) declare @llvm.aarch64.sve.smulh.u.nxv16i8(, , ) declare @llvm.aarch64.sve.smulh.u.nxv8i16(, , ) declare @llvm.aarch64.sve.smulh.u.nxv4i32(, , ) declare @llvm.aarch64.sve.smulh.u.nxv2i64(, , ) declare @llvm.aarch64.sve.umulh.u.nxv16i8(, , ) declare @llvm.aarch64.sve.umulh.u.nxv8i16(, , ) declare @llvm.aarch64.sve.umulh.u.nxv4i32(, , ) declare @llvm.aarch64.sve.umulh.u.nxv2i64(, , ) declare @llvm.aarch64.sve.pmul.nxv16i8(, ) declare @llvm.aarch64.sve.sqdmulh.nxv16i8(, ) declare @llvm.aarch64.sve.sqdmulh.nxv8i16(, ) declare @llvm.aarch64.sve.sqdmulh.nxv4i32(, ) declare @llvm.aarch64.sve.sqdmulh.nxv2i64(, ) declare @llvm.aarch64.sve.sqrdmulh.nxv16i8(, ) declare @llvm.aarch64.sve.sqrdmulh.nxv8i16(, ) declare @llvm.aarch64.sve.sqrdmulh.nxv4i32(, ) declare @llvm.aarch64.sve.sqrdmulh.nxv2i64(, )