# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:  known_sign_bits_smed3_0
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: known_sign_bits_smed3_0
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255
    ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
    %val:_(s32) = COPY $vgpr0
    %val0:_(s32) = G_SEXT_INREG %val, 8
    %val1:_(s32) = G_CONSTANT i32 -255
    %val2:_(s32) = G_CONSTANT i32 255
    %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    %inreg:_(s32) = G_SEXT_INREG %smed3, 9
    $vgpr0 = COPY %inreg

...

---
name:  known_sign_bits_smed3_1
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: known_sign_bits_smed3_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255
    ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2
    ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
    %val:_(s32) = COPY $vgpr0
    %val0:_(s32) = G_SEXT_INREG %val, 8
    %val1:_(s32) = G_CONSTANT i32 -255
    %val2:_(s32) = G_CONSTANT i32 255
    %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2
    %inreg:_(s32) = G_SEXT_INREG %smed3, 9
    $vgpr0 = COPY %inreg

...

---
name:  known_sign_bits_smed3_2
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: known_sign_bits_smed3_2
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -256
    ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 128
    ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0
    ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
    %val:_(s32) = COPY $vgpr0
    %val0:_(s32) = G_SEXT_INREG %val, 8
    %val1:_(s32) = G_CONSTANT i32 -256
    %val2:_(s32) = G_CONSTANT i32 128
    %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0
    %inreg:_(s32) = G_SEXT_INREG %smed3, 9
    $vgpr0 = COPY %inreg

...

---
name:  not_enough_sign_bits_smed3_0
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: not_enough_sign_bits_smed3_0
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 9
    ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
    ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
    ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
    %val:_(s32) = COPY $vgpr0
    %val0:_(s32) = G_SEXT_INREG %val, 8
    %val1:_(s32) = G_SEXT_INREG %val, 9
    %val2:_(s32) = G_SEXT_INREG %val, 9
    %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    %inreg:_(s32) = G_SEXT_INREG %smed3, 8
    $vgpr0 = COPY %inreg

...

---
name:  not_enough_sign_bits_smed3_1
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: not_enough_sign_bits_smed3_1
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 9
    ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
    ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
    ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
    %val:_(s32) = COPY $vgpr0
    %val0:_(s32) = G_SEXT_INREG %val, 9
    %val1:_(s32) = G_SEXT_INREG %val, 8
    %val2:_(s32) = G_SEXT_INREG %val, 9
    %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    %inreg:_(s32) = G_SEXT_INREG %smed3, 8
    $vgpr0 = COPY %inreg

...

---
name:  not_enough_sign_bits_smed3_2
legalized:       true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; CHECK-LABEL: name: not_enough_sign_bits_smed3_2
    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8
    ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
    ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
    ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
    %val:_(s32) = COPY $vgpr0
    %val0:_(s32) = G_SEXT_INREG %val, 8
    %val1:_(s32) = G_SEXT_INREG %val, 8
    %val2:_(s32) = G_SEXT_INREG %val, 9
    %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
    %inreg:_(s32) = G_SEXT_INREG %smed3, 8
    $vgpr0 = COPY %inreg

...