# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s

---
name: divergent_i1_phi_if_then
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: divergent_i1_phi_if_then
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C1]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.1
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI]](s1), [[C4]], [[C3]]
  ; GFX10-NEXT:   G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
    %3:_(s32) = COPY $vgpr2
    %4:_(s32) = COPY $vgpr3
    %5:_(s32) = G_CONSTANT i32 6
    %6:_(s1) = G_ICMP intpred(uge), %3(s32), %5
    %7:_(s32) = G_CONSTANT i32 0
    %8:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %4(s32), %7
    %9:sreg_32_xm0_xexec(s32) = SI_IF %8(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.1

  bb.1:
    successors: %bb.2(0x80000000)

    %10:_(s32) = G_CONSTANT i32 1
    %11:_(s1) = G_ICMP intpred(ult), %3(s32), %10

  bb.2:
    %12:_(s1) = G_PHI %6(s1), %bb.0, %11(s1), %bb.1
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32)
    %13:_(s32) = G_CONSTANT i32 2
    %14:_(s32) = G_CONSTANT i32 1
    %15:_(s32) = G_SELECT %12(s1), %14, %13
    G_STORE %15(s32), %2(p1) :: (store (s32), addrspace 1)
    S_ENDPGM 0
...

---
name: divergent_i1_phi_if_else
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: divergent_i1_phi_if_else
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s1) = G_PHI %10(s1), %bb.3, [[DEF]](s1), %bb.0
  ; GFX10-NEXT:   [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_ELSE [[SI_IF]](s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   successors: %bb.4(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C1]]
  ; GFX10-NEXT:   G_BR %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3:
  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]
  ; GFX10-NEXT:   G_BR %bb.1
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4:
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[PHI]](s1), %bb.1, [[ICMP1]](s1), %bb.2
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_ELSE]](s32)
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI1]](s1), [[C3]], [[C4]]
  ; GFX10-NEXT:   G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.3(0x40000000), %bb.1(0x40000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
    %3:_(s32) = COPY $vgpr2
    %4:_(s32) = COPY $vgpr3
    %5:_(s1) = G_IMPLICIT_DEF
    %6:_(s32) = G_CONSTANT i32 0
    %7:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %4(s32), %6
    %8:sreg_32_xm0_xexec(s32) = SI_IF %7(s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.3

  bb.1:
    successors: %bb.2(0x40000000), %bb.4(0x40000000)

    %9:_(s1) = G_PHI %10(s1), %bb.3, %5(s1), %bb.0
    %11:sreg_32_xm0_xexec(s32) = SI_ELSE %8(s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.2

  bb.2:
    successors: %bb.4(0x80000000)

    %12:_(s32) = G_CONSTANT i32 1
    %13:_(s1) = G_ICMP intpred(uge), %3(s32), %12
    G_BR %bb.4

  bb.3:
    successors: %bb.1(0x80000000)

    %14:_(s32) = G_CONSTANT i32 2
    %10:_(s1) = G_ICMP intpred(ult), %3(s32), %14
    G_BR %bb.1

  bb.4:
    %15:_(s1) = G_PHI %9(s1), %bb.1, %13(s1), %bb.2
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32)
    %16:_(s32) = G_CONSTANT i32 1
    %17:_(s32) = G_CONSTANT i32 2
    %18:_(s32) = G_SELECT %15(s1), %16, %17
    G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1)
    S_ENDPGM 0
...

---
name: loop_with_1break
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: loop_with_1break
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.3, [[C]](s32), %bb.0
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.3
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32)
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32)
  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)
  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C5]]
  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C5]]
  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C6]]
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3:
  ; GFX10-NEXT:   successors: %bb.4(0x04000000), %bb.1(0x7c000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.2, [[DEF]](s32), %bb.1
  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.2, [[C1]](s1), %bb.1
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4:
  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
  ; GFX10-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
    %3:_(s32) = COPY $vgpr2
    %4:_(s32) = COPY $vgpr3
    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
    %6:_(s32) = G_CONSTANT i32 0
    %7:_(s32) = G_IMPLICIT_DEF

  bb.1:
    successors: %bb.2(0x40000000), %bb.3(0x40000000)

    %8:_(s32) = G_PHI %9(s32), %bb.3, %6(s32), %bb.0
    %10:_(s32) = G_PHI %6(s32), %bb.0, %11(s32), %bb.3
    %12:_(s1) = G_CONSTANT i1 true
    %13:_(s64) = G_SEXT %10(s32)
    %14:_(s32) = G_CONSTANT i32 2
    %15:_(s64) = G_SHL %13, %14(s32)
    %16:_(p1) = G_PTR_ADD %5, %15(s64)
    %17:_(s32) = G_LOAD %16(p1) :: (load (s32), addrspace 1)
    %18:_(s32) = G_CONSTANT i32 0
    %19:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %17(s32), %18
    %20:sreg_32_xm0_xexec(s32) = SI_IF %19(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.2

  bb.2:
    successors: %bb.3(0x80000000)

    %21:_(s32) = G_CONSTANT i32 2
    %22:_(s64) = G_SHL %13, %21(s32)
    %23:_(p1) = G_PTR_ADD %2, %22(s64)
    %24:_(s32) = G_LOAD %23(p1) :: (load (s32), addrspace 1)
    %25:_(s32) = G_CONSTANT i32 1
    %26:_(s32) = G_ADD %24, %25
    G_STORE %26(s32), %23(p1) :: (store (s32), addrspace 1)
    %27:_(s32) = G_ADD %10, %25
    %28:_(s32) = G_CONSTANT i32 100
    %29:_(s1) = G_ICMP intpred(ult), %10(s32), %28

  bb.3:
    successors: %bb.4(0x04000000), %bb.1(0x7c000000)

    %11:_(s32) = G_PHI %27(s32), %bb.2, %7(s32), %bb.1
    %30:_(s1) = G_PHI %29(s1), %bb.2, %12(s1), %bb.1
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %20(s32)
    %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %30(s1), %8(s32)
    SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.4

  bb.4:
    %31:_(s32) = G_PHI %9(s32), %bb.3
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32)
    S_ENDPGM 0
...

---
name: loop_with_2breaks
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: loop_with_2breaks
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.3, [[C]](s32), %bb.0
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.3
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32)
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)
  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)
  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C6]]
  ; GFX10-NEXT:   [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3:
  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI %32(s32), %bb.5, [[DEF]](s32), %bb.1
  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI %34(s1), %bb.5, [[C1]](s1), %bb.1
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.6
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C7]](s32)
  ; GFX10-NEXT:   [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL2]](s64)
  ; GFX10-NEXT:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[C8]]
  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD2]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C8]]
  ; GFX10-NEXT:   [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C9]]
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5:
  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.4, [[DEF]](s32), %bb.2
  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:_(s1) = G_PHI [[ICMP2]](s1), %bb.4, [[C4]](s1), %bb.2
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)
  ; GFX10-NEXT:   G_BR %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.6:
  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32)
  ; GFX10-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
    %3:_(s32) = COPY $vgpr2
    %4:_(s32) = COPY $vgpr3
    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
    %6:_(s32) = COPY $vgpr4
    %7:_(s32) = COPY $vgpr5
    %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
    %9:_(s32) = G_CONSTANT i32 0
    %10:_(s32) = G_IMPLICIT_DEF

  bb.1:
    successors: %bb.2(0x40000000), %bb.3(0x40000000)

    %11:_(s32) = G_PHI %12(s32), %bb.3, %9(s32), %bb.0
    %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.3
    %15:_(s1) = G_CONSTANT i1 true
    %16:_(s64) = G_SEXT %13(s32)
    %17:_(s32) = G_CONSTANT i32 2
    %18:_(s64) = G_SHL %16, %17(s32)
    %19:_(p1) = G_PTR_ADD %5, %18(s64)
    %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)
    %21:_(s32) = G_CONSTANT i32 0
    %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21
    %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.2

  bb.2:
    successors: %bb.4(0x40000000), %bb.5(0x40000000)

    %24:_(s1) = G_CONSTANT i1 true
    %25:_(s32) = G_CONSTANT i32 2
    %26:_(s64) = G_SHL %16, %25(s32)
    %27:_(p1) = G_PTR_ADD %8, %26(s64)
    %28:_(s32) = G_LOAD %27(p1) :: (load (s32), addrspace 1)
    %29:_(s32) = G_CONSTANT i32 0
    %30:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %28(s32), %29
    %31:sreg_32_xm0_xexec(s32) = SI_IF %30(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.4

  bb.3:
    successors: %bb.6(0x04000000), %bb.1(0x7c000000)

    %14:_(s32) = G_PHI %32(s32), %bb.5, %10(s32), %bb.1
    %33:_(s1) = G_PHI %34(s1), %bb.5, %15(s1), %bb.1
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)
    %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %33(s1), %11(s32)
    SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.6

  bb.4:
    successors: %bb.5(0x80000000)

    %35:_(s32) = G_CONSTANT i32 2
    %36:_(s64) = G_SHL %16, %35(s32)
    %37:_(p1) = G_PTR_ADD %2, %36(s64)
    %38:_(s32) = G_LOAD %37(p1) :: (load (s32), addrspace 1)
    %39:_(s32) = G_CONSTANT i32 1
    %40:_(s32) = G_ADD %38, %39
    G_STORE %40(s32), %37(p1) :: (store (s32), addrspace 1)
    %41:_(s32) = G_ADD %13, %39
    %42:_(s32) = G_CONSTANT i32 100
    %43:_(s1) = G_ICMP intpred(ult), %13(s32), %42

  bb.5:
    successors: %bb.3(0x80000000)

    %32:_(s32) = G_PHI %41(s32), %bb.4, %10(s32), %bb.2
    %34:_(s1) = G_PHI %43(s1), %bb.4, %24(s1), %bb.2
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32)
    G_BR %bb.3

  bb.6:
    %44:_(s32) = G_PHI %12(s32), %bb.3
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %44(s32)
    S_ENDPGM 0
...

---
name: loop_with_3breaks
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: loop_with_3breaks
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
  ; GFX10-NEXT:   [[MV3:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.3, [[C]](s32), %bb.0
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.3
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32)
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)
  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)
  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C6]]
  ; GFX10-NEXT:   [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3:
  ; GFX10-NEXT:   successors: %bb.8(0x04000000), %bb.1(0x7c000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI %35(s32), %bb.5, [[DEF]](s32), %bb.1
  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI %37(s1), %bb.5, [[C1]](s1), %bb.1
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.8
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4:
  ; GFX10-NEXT:   successors: %bb.6(0x40000000), %bb.7(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C8]](s32)
  ; GFX10-NEXT:   [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV3]], [[SHL2]](s64)
  ; GFX10-NEXT:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD2]](s32), [[C9]]
  ; GFX10-NEXT:   [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP2]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.6
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5:
  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI %46(s32), %bb.7, [[DEF]](s32), %bb.2
  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:_(s1) = G_PHI %47(s1), %bb.7, [[C4]](s1), %bb.2
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)
  ; GFX10-NEXT:   G_BR %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.6:
  ; GFX10-NEXT:   successors: %bb.7(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C10]](s32)
  ; GFX10-NEXT:   [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL3]](s64)
  ; GFX10-NEXT:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[C11]]
  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD3]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C11]]
  ; GFX10-NEXT:   [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
  ; GFX10-NEXT:   [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C12]]
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.7:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.6, [[DEF]](s32), %bb.4
  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:_(s1) = G_PHI [[ICMP3]](s1), %bb.6, [[C7]](s1), %bb.4
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)
  ; GFX10-NEXT:   G_BR %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.8:
  ; GFX10-NEXT:   [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI8]](s32)
  ; GFX10-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
    %3:_(s32) = COPY $vgpr2
    %4:_(s32) = COPY $vgpr3
    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
    %6:_(s32) = COPY $vgpr4
    %7:_(s32) = COPY $vgpr5
    %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
    %9:_(s32) = COPY $vgpr6
    %10:_(s32) = COPY $vgpr7
    %11:_(p1) = G_MERGE_VALUES %9(s32), %10(s32)
    %12:_(s32) = G_CONSTANT i32 0
    %13:_(s32) = G_IMPLICIT_DEF

  bb.1:
    successors: %bb.2(0x40000000), %bb.3(0x40000000)

    %14:_(s32) = G_PHI %15(s32), %bb.3, %12(s32), %bb.0
    %16:_(s32) = G_PHI %12(s32), %bb.0, %17(s32), %bb.3
    %18:_(s1) = G_CONSTANT i1 true
    %19:_(s64) = G_SEXT %16(s32)
    %20:_(s32) = G_CONSTANT i32 2
    %21:_(s64) = G_SHL %19, %20(s32)
    %22:_(p1) = G_PTR_ADD %5, %21(s64)
    %23:_(s32) = G_LOAD %22(p1) :: (load (s32), addrspace 1)
    %24:_(s32) = G_CONSTANT i32 0
    %25:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %23(s32), %24
    %26:sreg_32_xm0_xexec(s32) = SI_IF %25(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.2

  bb.2:
    successors: %bb.4(0x40000000), %bb.5(0x40000000)

    %27:_(s1) = G_CONSTANT i1 true
    %28:_(s32) = G_CONSTANT i32 2
    %29:_(s64) = G_SHL %19, %28(s32)
    %30:_(p1) = G_PTR_ADD %8, %29(s64)
    %31:_(s32) = G_LOAD %30(p1) :: (load (s32), addrspace 1)
    %32:_(s32) = G_CONSTANT i32 0
    %33:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %31(s32), %32
    %34:sreg_32_xm0_xexec(s32) = SI_IF %33(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.4

  bb.3:
    successors: %bb.8(0x04000000), %bb.1(0x7c000000)

    %17:_(s32) = G_PHI %35(s32), %bb.5, %13(s32), %bb.1
    %36:_(s1) = G_PHI %37(s1), %bb.5, %18(s1), %bb.1
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %26(s32)
    %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %36(s1), %14(s32)
    SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.8

  bb.4:
    successors: %bb.6(0x40000000), %bb.7(0x40000000)

    %38:_(s1) = G_CONSTANT i1 true
    %39:_(s32) = G_CONSTANT i32 2
    %40:_(s64) = G_SHL %19, %39(s32)
    %41:_(p1) = G_PTR_ADD %11, %40(s64)
    %42:_(s32) = G_LOAD %41(p1) :: (load (s32), addrspace 1)
    %43:_(s32) = G_CONSTANT i32 0
    %44:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %42(s32), %43
    %45:sreg_32_xm0_xexec(s32) = SI_IF %44(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.6

  bb.5:
    successors: %bb.3(0x80000000)

    %35:_(s32) = G_PHI %46(s32), %bb.7, %13(s32), %bb.2
    %37:_(s1) = G_PHI %47(s1), %bb.7, %27(s1), %bb.2
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)
    G_BR %bb.3

  bb.6:
    successors: %bb.7(0x80000000)

    %48:_(s32) = G_CONSTANT i32 2
    %49:_(s64) = G_SHL %19, %48(s32)
    %50:_(p1) = G_PTR_ADD %2, %49(s64)
    %51:_(s32) = G_LOAD %50(p1) :: (load (s32), addrspace 1)
    %52:_(s32) = G_CONSTANT i32 1
    %53:_(s32) = G_ADD %51, %52
    G_STORE %53(s32), %50(p1) :: (store (s32), addrspace 1)
    %54:_(s32) = G_ADD %16, %52
    %55:_(s32) = G_CONSTANT i32 100
    %56:_(s1) = G_ICMP intpred(ult), %16(s32), %55

  bb.7:
    successors: %bb.5(0x80000000)

    %46:_(s32) = G_PHI %54(s32), %bb.6, %13(s32), %bb.4
    %47:_(s1) = G_PHI %56(s1), %bb.6, %38(s1), %bb.4
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %45(s32)
    G_BR %bb.5

  bb.8:
    %57:_(s32) = G_PHI %15(s32), %bb.3
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %57(s32)
    S_ENDPGM 0
...

---
name: loop_with_div_break_with_body
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: loop_with_div_break_with_body
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32)
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   successors: %bb.4(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
  ; GFX10-NEXT:   G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   G_BR %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3:
  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32)
  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)
  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]]
  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)
  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C7]]
  ; GFX10-NEXT:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C8]]
  ; GFX10-NEXT:   G_BR %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4:
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)
  ; GFX10-NEXT:   S_ENDPGM 0
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5:
  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1
  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C5]](s1), %bb.3, [[C1]](s1), %bb.1
  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.3, [[C1]](s1), %bb.1
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI4]](s1), [[PHI]](s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.6
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.6:
  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[PHI3]](s1), %bb.5
  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.5
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32)
  ; GFX10-NEXT:   [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI5]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.2
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
    %3:_(s32) = COPY $vgpr2
    %4:_(s32) = COPY $vgpr3
    %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
    %6:_(s32) = COPY $vgpr4
    %7:_(s32) = COPY $vgpr5
    %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
    %9:_(s32) = G_CONSTANT i32 0
    %10:_(s32) = G_IMPLICIT_DEF

  bb.1:
    successors: %bb.3(0x40000000), %bb.5(0x40000000)

    %11:_(s32) = G_PHI %12(s32), %bb.5, %9(s32), %bb.0
    %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.5
    %15:_(s1) = G_CONSTANT i1 true
    %16:_(s64) = G_SEXT %13(s32)
    %17:_(s32) = G_CONSTANT i32 2
    %18:_(s64) = G_SHL %16, %17(s32)
    %19:_(p1) = G_PTR_ADD %5, %18(s64)
    %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)
    %21:_(s32) = G_CONSTANT i32 0
    %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21
    %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.3

  bb.2:
    successors: %bb.4(0x80000000)

    %24:_(s32) = G_CONSTANT i32 10
    G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1)
    G_BR %bb.4

  bb.3:
    successors: %bb.5(0x80000000)

    %25:_(s1) = G_CONSTANT i1 false
    %26:_(s32) = G_CONSTANT i32 2
    %27:_(s64) = G_SHL %16, %26(s32)
    %28:_(p1) = G_PTR_ADD %2, %27(s64)
    %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1)
    %30:_(s32) = G_CONSTANT i32 1
    %31:_(s32) = G_ADD %29, %30
    G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1)
    %32:_(s32) = G_ADD %13, %30
    %33:_(s32) = G_CONSTANT i32 100
    %34:_(s1) = G_ICMP intpred(ult), %13(s32), %33
    G_BR %bb.5

  bb.4:
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)
    S_ENDPGM 0

  bb.5:
    successors: %bb.6(0x04000000), %bb.1(0x7c000000)

    %14:_(s32) = G_PHI %32(s32), %bb.3, %10(s32), %bb.1
    %36:_(s1) = G_PHI %25(s1), %bb.3, %15(s1), %bb.1
    %37:_(s1) = G_PHI %34(s1), %bb.3, %15(s1), %bb.1
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)
    %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32)
    SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.6

  bb.6:
    successors: %bb.2(0x40000000), %bb.4(0x40000000)

    %38:sreg_32_xm0_xexec(s1) = G_PHI %36(s1), %bb.5
    %39:_(s32) = G_PHI %12(s32), %bb.5
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %39(s32)
    %35:sreg_32_xm0_xexec(s32) = SI_IF %38(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.2
...

---
name: irreducible_cfg
legalized: true
tracksRegLiveness: true
body: |
  ; GFX10-LABEL: name: irreducible_cfg
  ; GFX10: bb.0:
  ; GFX10-NEXT:   successors: %bb.7(0x80000000)
  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY4]](s32), [[COPY1]]
  ; GFX10-NEXT:   G_BR %bb.7
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.1:
  ; GFX10-NEXT:   successors: %bb.3(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY4]](s32), [[COPY]]
  ; GFX10-NEXT:   G_BR %bb.3
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.2:
  ; GFX10-NEXT:   successors: %bb.4(0x40000000), %bb.7(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:_(s1) = G_PHI %12(s1), %bb.6, [[DEF]](s1), %bb.7
  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s1) = G_PHI %12(s1), %bb.6, %14(s1), %bb.7
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI1]](s1), %17(s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.4
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.3:
  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.3(0x7c000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1, %19(s32), %bb.3
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI2]](s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT1]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.6
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.4:
  ; GFX10-NEXT:   successors: %bb.5(0x04000000), %bb.7(0x7c000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INTRINSIC_CONVERGENT]](s32)
  ; GFX10-NEXT:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY5]](s32), [[COPY]]
  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C2]]
  ; GFX10-NEXT:   [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[XOR]]
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[OR]](s1), %25(s32)
  ; GFX10-NEXT:   SI_LOOP [[INTRINSIC_CONVERGENT2]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.5
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.5:
  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[ICMP2]](s1), %bb.4
  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT2]](s32), %bb.4
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[COPY3]], [[COPY2]]
  ; GFX10-NEXT:   [[INTRINSIC_CONVERGENT3:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SELECT]](s32)
  ; GFX10-NEXT:   $sgpr0 = COPY [[INTRINSIC_CONVERGENT3]](s32)
  ; GFX10-NEXT:   SI_RETURN_TO_EPILOG implicit $sgpr0
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.6:
  ; GFX10-NEXT:   successors: %bb.2(0x80000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT1]](s32), %bb.3
  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
  ; GFX10-NEXT:   G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32)
  ; GFX10-NEXT:   G_BR %bb.2
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT: bb.7:
  ; GFX10-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GFX10-NEXT: {{  $}}
  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT2]](s32), %bb.4, [[PHI6]](s32), %bb.2, [[C]](s32), %bb.0
  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.4, [[INTRINSIC_CONVERGENT]](s32), %bb.2, [[C]](s32), %bb.0
  ; GFX10-NEXT:   [[PHI8:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[ICMP]](s1), %bb.0, [[PHI]](s1), %bb.2, [[C2]](s1), %bb.4
  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI8]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
  ; GFX10-NEXT:   G_BR %bb.1
  bb.0:
    successors: %bb.7(0x80000000)
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5

    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = COPY $vgpr2
    %3:_(s32) = COPY $vgpr3
    %4:_(s32) = COPY $vgpr4
    %5:_(s32) = COPY $vgpr5
    %6:_(s32) = G_CONSTANT i32 0
    %7:_(s1) = G_IMPLICIT_DEF
    %8:_(s1) = G_ICMP intpred(sgt), %4(s32), %1
    G_BR %bb.7

  bb.1:
    successors: %bb.3(0x80000000)

    %9:_(s32) = G_CONSTANT i32 0
    %10:_(s1) = G_ICMP intpred(sle), %4(s32), %0
    G_BR %bb.3

  bb.2:
    successors: %bb.4(0x40000000), %bb.7(0x40000000)

    %11:_(s1) = G_PHI %12(s1), %bb.6, %7(s1), %bb.7
    %13:_(s1) = G_PHI %12(s1), %bb.6, %14(s1), %bb.7
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
    %16:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %13(s1), %17(s32)
    SI_LOOP %16(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.4

  bb.3:
    successors: %bb.6(0x04000000), %bb.3(0x7c000000)

    %18:_(s32) = G_PHI %9(s32), %bb.1, %19(s32), %bb.3
    %19:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %10(s1), %18(s32)
    SI_LOOP %19(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.6

  bb.4:
    successors: %bb.5(0x04000000), %bb.7(0x7c000000)

    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %16(s32)
    %20:_(s1) = G_ICMP intpred(sgt), %5(s32), %0
    %21:_(s1) = G_CONSTANT i1 true
    %22:_(s1) = G_XOR %8, %21
    %23:_(s1) = G_OR %20, %22
    %24:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %23(s1), %25(s32)
    SI_LOOP %24(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.5

  bb.5:
    %26:_(s1) = G_PHI %20(s1), %bb.4
    %27:_(s32) = G_PHI %24(s32), %bb.4
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32)
    %28:_(s32) = G_SELECT %26(s1), %3, %2
    %29:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %28(s32)
    $sgpr0 = COPY %29(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

  bb.6:
    successors: %bb.2(0x80000000)

    %30:_(s32) = G_PHI %19(s32), %bb.3
    %12:_(s1) = G_CONSTANT i1 false
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %30(s32)
    G_BR %bb.2

  bb.7:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)

    %25:_(s32) = G_PHI %24(s32), %bb.4, %25(s32), %bb.2, %6(s32), %bb.0
    %17:_(s32) = G_PHI %6(s32), %bb.4, %16(s32), %bb.2, %6(s32), %bb.0
    %31:sreg_32_xm0_xexec(s1) = G_PHI %8(s1), %bb.0, %11(s1), %bb.2, %21(s1), %bb.4
    %14:_(s1) = G_CONSTANT i1 true
    %15:sreg_32_xm0_xexec(s32) = SI_IF %31(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
    G_BR %bb.1
...