; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=hexagon < %s | FileCheck %s define i32 @f0(ptr %a0, i32 %a1) #0 { ; CHECK-LABEL: f0: ; CHECK: // %bb.0: ; CHECK-NEXT: { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r1 = asl(r1,#2) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = tstbit(r0,r1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r0 = mux(p0,#-1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: } %v0 = load <2 x i1>, ptr %a0 %v1 = extractelement <2 x i1> %v0, i32 %a1 %v2 = sext i1 %v1 to i32 ret i32 %v2 } define i32 @f1(ptr %a0, i32 %a1) #0 { ; CHECK-LABEL: f1: ; CHECK: // %bb.0: ; CHECK-NEXT: { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r1 = asl(r1,#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = tstbit(r0,r1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r0 = mux(p0,#-1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: } %v0 = load <4 x i1>, ptr %a0 %v1 = extractelement <4 x i1> %v0, i32 %a1 %v2 = sext i1 %v1 to i32 ret i32 %v2 } define i32 @f2(ptr %a0, i32 %a1) #0 { ; CHECK-LABEL: f2: ; CHECK: // %bb.0: ; CHECK-NEXT: { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = tstbit(r0,r1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r0 = mux(p0,#-1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: } %v0 = load <8 x i1>, ptr %a0 %v1 = extractelement <8 x i1> %v0, i32 %a1 %v2 = sext i1 %v1 to i32 ret i32 %v2 } attributes #0 = { nounwind "target-features"="-packets" }