; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8>)

define <16 x i16> @lasx_xvexth_h_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_h_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.h.b $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8> %va)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvexth.w.h(<16 x i16>)

define <8 x i32> @lasx_xvexth_w_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_w_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.w.h $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvexth.w.h(<16 x i16> %va)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvexth.d.w(<8 x i32>)

define <4 x i64> @lasx_xvexth_d_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.d.w $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.d.w(<8 x i32> %va)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvexth.q.d(<4 x i64>)

define <4 x i64> @lasx_xvexth_q_d(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_q_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.q.d $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.q.d(<4 x i64> %va)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvexth.hu.bu(<32 x i8>)

define <16 x i16> @lasx_xvexth_hu_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_hu_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.hu.bu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvexth.hu.bu(<32 x i8> %va)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvexth.wu.hu(<16 x i16>)

define <8 x i32> @lasx_xvexth_wu_hu(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_wu_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.wu.hu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvexth.wu.hu(<16 x i16> %va)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvexth.du.wu(<8 x i32>)

define <4 x i64> @lasx_xvexth_du_wu(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_du_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.du.wu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.du.wu(<8 x i32> %va)
  ret <4 x i64> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvexth.qu.du(<4 x i64>)

define <4 x i64> @lasx_xvexth_qu_du(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvexth_qu_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvexth.qu.du $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvexth.qu.du(<4 x i64> %va)
  ret <4 x i64> %res
}