; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <8 x float> @llvm.loongarch.lasx.xvffint.s.w(<8 x i32>)

define <8 x float> @lasx_xvffint_s_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvffint_s_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffint.s.w $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x float> @llvm.loongarch.lasx.xvffint.s.w(<8 x i32> %va)
  ret <8 x float> %res
}

declare <4 x double> @llvm.loongarch.lasx.xvffint.d.l(<4 x i64>)

define <4 x double> @lasx_xvffint_d_l(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvffint_d_l:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffint.d.l $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x double> @llvm.loongarch.lasx.xvffint.d.l(<4 x i64> %va)
  ret <4 x double> %res
}

declare <8 x float> @llvm.loongarch.lasx.xvffint.s.wu(<8 x i32>)

define <8 x float> @lasx_xvffint_s_wu(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvffint_s_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffint.s.wu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x float> @llvm.loongarch.lasx.xvffint.s.wu(<8 x i32> %va)
  ret <8 x float> %res
}

declare <4 x double> @llvm.loongarch.lasx.xvffint.d.lu(<4 x i64>)

define <4 x double> @lasx_xvffint_d_lu(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvffint_d_lu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffint.d.lu $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x double> @llvm.loongarch.lasx.xvffint.d.lu(<4 x i64> %va)
  ret <4 x double> %res
}

declare <4 x double> @llvm.loongarch.lasx.xvffintl.d.w(<8 x i32>)

define <4 x double> @lasx_xvffintl_d_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvffintl_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffintl.d.w $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x double> @llvm.loongarch.lasx.xvffintl.d.w(<8 x i32> %va)
  ret <4 x double> %res
}

declare <4 x double> @llvm.loongarch.lasx.xvffinth.d.w(<8 x i32>)

define <4 x double> @lasx_xvffinth_d_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvffinth_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffinth.d.w $xr0, $xr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x double> @llvm.loongarch.lasx.xvffinth.d.w(<8 x i32> %va)
  ret <4 x double> %res
}

declare <8 x float> @llvm.loongarch.lasx.xvffint.s.l(<4 x i64>, <4 x i64>)

define <8 x float> @lasx_xvffint_s_l(<4 x i64> %va, <4 x i64> %vb) nounwind {
; CHECK-LABEL: lasx_xvffint_s_l:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvffint.s.l $xr0, $xr0, $xr1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x float> @llvm.loongarch.lasx.xvffint.s.l(<4 x i64> %va, <4 x i64> %vb)
  ret <8 x float> %res
}