; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <32 x i8> @llvm.loongarch.lasx.xvreplgr2vr.b(i32)

define <32 x i8> @lasx_xvreplgr2vr_b(i32 %a) nounwind {
; CHECK-LABEL: lasx_xvreplgr2vr_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvreplgr2vr.b $xr0, $a0
; CHECK-NEXT:    ret
entry:
  %res = call <32 x i8> @llvm.loongarch.lasx.xvreplgr2vr.b(i32 %a)
  ret <32 x i8> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvreplgr2vr.h(i32)

define <16 x i16> @lasx_xvreplgr2vr_h(i32 %a) nounwind {
; CHECK-LABEL: lasx_xvreplgr2vr_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvreplgr2vr.h $xr0, $a0
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvreplgr2vr.h(i32 %a)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32)

define <8 x i32> @lasx_xvreplgr2vr_w(i32 %a) nounwind {
; CHECK-LABEL: lasx_xvreplgr2vr_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvreplgr2vr.w $xr0, $a0
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32 %a)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64)

define <4 x i64> @lasx_xvreplgr2vr_d(i64 %a) nounwind {
; CHECK-LABEL: lasx_xvreplgr2vr_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvreplgr2vr.d $xr0, $a0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64 %a)
  ret <4 x i64> %res
}