; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32)

define <16 x i16> @lasx_xvsllwil_h_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvsllwil_h_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvsllwil.h.b $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8> %va, i32 1)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvsllwil.w.h(<16 x i16>, i32)

define <8 x i32> @lasx_xvsllwil_w_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvsllwil_w_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvsllwil.w.h $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvsllwil.w.h(<16 x i16> %va, i32 1)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvsllwil.d.w(<8 x i32>, i32)

define <4 x i64> @lasx_xvsllwil_d_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvsllwil_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvsllwil.d.w $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvsllwil.d.w(<8 x i32> %va, i32 1)
  ret <4 x i64> %res
}

declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.hu.bu(<32 x i8>, i32)

define <16 x i16> @lasx_xvsllwil_hu_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvsllwil_hu_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvsllwil.hu.bu $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i16> @llvm.loongarch.lasx.xvsllwil.hu.bu(<32 x i8> %va, i32 1)
  ret <16 x i16> %res
}

declare <8 x i32> @llvm.loongarch.lasx.xvsllwil.wu.hu(<16 x i16>, i32)

define <8 x i32> @lasx_xvsllwil_wu_hu(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvsllwil_wu_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvsllwil.wu.hu $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvsllwil.wu.hu(<16 x i16> %va, i32 1)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvsllwil.du.wu(<8 x i32>, i32)

define <4 x i64> @lasx_xvsllwil_du_wu(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvsllwil_du_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvsllwil.du.wu $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvsllwil.du.wu(<8 x i32> %va, i32 1)
  ret <4 x i64> %res
}