; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <4 x float> @llvm.loongarch.lsx.vffint.s.w(<4 x i32>)

define <4 x float> @lsx_vffint_s_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vffint_s_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffint.s.w $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x float> @llvm.loongarch.lsx.vffint.s.w(<4 x i32> %va)
  ret <4 x float> %res
}

declare <2 x double> @llvm.loongarch.lsx.vffint.d.l(<2 x i64>)

define <2 x double> @lsx_vffint_d_l(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vffint_d_l:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffint.d.l $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x double> @llvm.loongarch.lsx.vffint.d.l(<2 x i64> %va)
  ret <2 x double> %res
}

declare <4 x float> @llvm.loongarch.lsx.vffint.s.wu(<4 x i32>)

define <4 x float> @lsx_vffint_s_wu(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vffint_s_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffint.s.wu $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <4 x float> @llvm.loongarch.lsx.vffint.s.wu(<4 x i32> %va)
  ret <4 x float> %res
}

declare <2 x double> @llvm.loongarch.lsx.vffint.d.lu(<2 x i64>)

define <2 x double> @lsx_vffint_d_lu(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vffint_d_lu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffint.d.lu $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x double> @llvm.loongarch.lsx.vffint.d.lu(<2 x i64> %va)
  ret <2 x double> %res
}

declare <2 x double> @llvm.loongarch.lsx.vffintl.d.w(<4 x i32>)

define <2 x double> @lsx_vffintl_d_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vffintl_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffintl.d.w $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x double> @llvm.loongarch.lsx.vffintl.d.w(<4 x i32> %va)
  ret <2 x double> %res
}

declare <2 x double> @llvm.loongarch.lsx.vffinth.d.w(<4 x i32>)

define <2 x double> @lsx_vffinth_d_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vffinth_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffinth.d.w $vr0, $vr0
; CHECK-NEXT:    ret
entry:
  %res = call <2 x double> @llvm.loongarch.lsx.vffinth.d.w(<4 x i32> %va)
  ret <2 x double> %res
}

declare <4 x float> @llvm.loongarch.lsx.vffint.s.l(<2 x i64>, <2 x i64>)

define <4 x float> @lsx_vffint_s_l(<2 x i64> %va, <2 x i64> %vb) nounwind {
; CHECK-LABEL: lsx_vffint_s_l:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vffint.s.l $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x float> @llvm.loongarch.lsx.vffint.s.l(<2 x i64> %va, <2 x i64> %vb)
  ret <4 x float> %res
}